
Toan V. Tran
Examiner (ID: 4400)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2816, 2504, 3621 |
| Total Applications | 1179 |
| Issued Applications | 1083 |
| Pending Applications | 23 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4189446
[patent_doc_number] => 06020774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Gated clock tree synthesis method for the logic design'
[patent_app_type] => 1
[patent_app_number] => 9/121296
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/020/06020774.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121296 | Gated clock tree synthesis method for the logic design | Jul 22, 1998 | Issued |
Array
(
[id] => 4225346
[patent_doc_number] => 06087873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Precision hysteresis circuit'
[patent_app_type] => 1
[patent_app_number] => 9/119945
[patent_app_country] => US
[patent_app_date] => 1998-07-21
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/119945 | Precision hysteresis circuit | Jul 20, 1998 | Issued |
Array
(
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[patent_doc_number] => 06057724
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Method and apparatus for synchronized clock distribution'
[patent_app_type] => 1
[patent_app_number] => 9/114732
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[patent_app_date] => 1998-07-13
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[firstpage_image] =>[orig_patent_app_number] => 114732
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/114732 | Method and apparatus for synchronized clock distribution | Jul 12, 1998 | Issued |
Array
(
[id] => 4077733
[patent_doc_number] => 06069509
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[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Output stage with slewing control means'
[patent_app_type] => 1
[patent_app_number] => 9/111612
[patent_app_country] => US
[patent_app_date] => 1998-07-07
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[firstpage_image] =>[orig_patent_app_number] => 111612
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111612 | Output stage with slewing control means | Jul 6, 1998 | Issued |
Array
(
[id] => 4121935
[patent_doc_number] => 06046615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Level detection circuit'
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[patent_app_number] => 9/094825
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/094825 | Level detection circuit | Jun 14, 1998 | Issued |
Array
(
[id] => 4191713
[patent_doc_number] => 06150851
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[patent_issue_date] => 2000-11-21
[patent_title] => 'Charge transfer amplifier circuit, voltage comparator, and sense amplifier'
[patent_app_type] => 1
[patent_app_number] => 9/092465
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/092465 | Charge transfer amplifier circuit, voltage comparator, and sense amplifier | Jun 4, 1998 | Issued |
Array
(
[id] => 4121881
[patent_doc_number] => 06046611
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[patent_issue_date] => 2000-04-04
[patent_title] => 'Semiconductor circuit device with receiver circuit'
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[firstpage_image] =>[orig_patent_app_number] => 089452
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/089452 | Semiconductor circuit device with receiver circuit | Jun 2, 1998 | Issued |
Array
(
[id] => 4072982
[patent_doc_number] => 06008681
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[patent_issue_date] => 1999-12-28
[patent_title] => 'Method and apparatus for deriving power from a clock signal coupled through a transformer'
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[patent_app_number] => 9/088629
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[pdf_file] => patents/06/008/06008681.pdf
[firstpage_image] =>[orig_patent_app_number] => 088629
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088629 | Method and apparatus for deriving power from a clock signal coupled through a transformer | Jun 1, 1998 | Issued |
Array
(
[id] => 3946966
[patent_doc_number] => 05973551
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Abnormal current detection circuit and load drive circuit including the same'
[patent_app_type] => 1
[patent_app_number] => 9/087636
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Array
(
[id] => 4224461
[patent_doc_number] => 06111437
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[patent_title] => 'Wide common-mode differential receiver with precision input referred offset'
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[patent_app_number] => 9/087297
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/087297 | Wide common-mode differential receiver with precision input referred offset | May 28, 1998 | Issued |
Array
(
[id] => 3946462
[patent_doc_number] => 05973517
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[patent_title] => 'Speed-enhancing comparator with cascaded inventors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086248 | Speed-enhancing comparator with cascaded inventors | May 27, 1998 | Issued |
Array
(
[id] => 4211866
[patent_doc_number] => 06078208
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[patent_issue_date] => 2000-06-20
[patent_title] => 'Precision temperature sensor integrated circuit'
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Array
(
[id] => 4214391
[patent_doc_number] => 06028472
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[patent_title] => 'Temperature sensing circuit, driving apparatus, and printer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083065 | Temperature sensing circuit, driving apparatus, and printer | May 20, 1998 | Issued |
Array
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[id] => 4186582
[patent_doc_number] => 06037807
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[patent_title] => 'Synchronous sense amplifier with temperature and voltage compensated translator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/080710 | Synchronous sense amplifier with temperature and voltage compensated translator | May 17, 1998 | Issued |
Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071352 | CMOS delay circuit | Apr 29, 1998 | Issued |