Search

Toan V. Tran

Examiner (ID: 4400)

Most Active Art Unit
2816
Art Unit(s)
2899, 2816, 2504, 3621
Total Applications
1179
Issued Applications
1083
Pending Applications
23
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1456210 [patent_doc_number] => 06462589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Bus capture circuit for single-ended and differential signals' [patent_app_type] => B2 [patent_app_number] => 09/990751 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2374 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462589.pdf [firstpage_image] =>[orig_patent_app_number] => 09990751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990751
Bus capture circuit for single-ended and differential signals Nov 15, 2001 Issued
Array ( [id] => 7645042 [patent_doc_number] => 06472931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method and apparatus that models neural transmission to amplify a capacitively-coupled input signal' [patent_app_type] => B1 [patent_app_number] => 09/991475 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4362 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472931.pdf [firstpage_image] =>[orig_patent_app_number] => 09991475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/991475
Method and apparatus that models neural transmission to amplify a capacitively-coupled input signal Nov 15, 2001 Issued
Array ( [id] => 5933978 [patent_doc_number] => 20020060589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Driver and method for switching applications' [patent_app_type] => new [patent_app_number] => 10/003772 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12419 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060589.pdf [firstpage_image] =>[orig_patent_app_number] => 10003772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003772
Driver and method for switching applications Nov 14, 2001 Issued
Array ( [id] => 6124589 [patent_doc_number] => 20020075054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Read gain offset trim without feedback loop' [patent_app_type] => new [patent_app_number] => 09/992905 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2698 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075054.pdf [firstpage_image] =>[orig_patent_app_number] => 09992905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992905
Read gain offset trim without feedback loop Nov 13, 2001 Abandoned
Array ( [id] => 6350303 [patent_doc_number] => 20020057114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Circuit for driving gate of IGBT inverter' [patent_app_type] => new [patent_app_number] => 09/987472 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3385 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20020057114.pdf [firstpage_image] =>[orig_patent_app_number] => 09987472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987472
Circuit for driving gate of IGBT inverter Nov 13, 2001 Issued
Array ( [id] => 1387694 [patent_doc_number] => 06559700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/986144 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 12801 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559700.pdf [firstpage_image] =>[orig_patent_app_number] => 09986144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986144
Semiconductor integrated circuit Nov 6, 2001 Issued
Array ( [id] => 5965215 [patent_doc_number] => 20020089355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Differential comparison circuit' [patent_app_type] => new [patent_app_number] => 09/992335 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3470 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20020089355.pdf [firstpage_image] =>[orig_patent_app_number] => 09992335 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992335
Differential comparison circuit Nov 5, 2001 Issued
Array ( [id] => 6510925 [patent_doc_number] => 20020135402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'SAMPLE-AND-HOLD CIRCUIT AND A/D CONVERTER' [patent_app_type] => new [patent_app_number] => 09/992334 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7133 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20020135402.pdf [firstpage_image] =>[orig_patent_app_number] => 09992334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992334
Sample-and-hold circuit and A/D converter Nov 5, 2001 Issued
Array ( [id] => 1453039 [patent_doc_number] => 06456156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and device for the open-load diagnosis of a switching stage' [patent_app_type] => B1 [patent_app_number] => 10/011876 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3599 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456156.pdf [firstpage_image] =>[orig_patent_app_number] => 10011876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011876
Method and device for the open-load diagnosis of a switching stage Nov 4, 2001 Issued
Array ( [id] => 1383069 [patent_doc_number] => 06563363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Switched capacitor comparator network' [patent_app_type] => B1 [patent_app_number] => 10/004909 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1770 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563363.pdf [firstpage_image] =>[orig_patent_app_number] => 10004909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004909
Switched capacitor comparator network Nov 1, 2001 Issued
Array ( [id] => 6388847 [patent_doc_number] => 20020180493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'BIPOLAR COMPARATOR' [patent_app_type] => new [patent_app_number] => 10/012178 [patent_app_country] => US [patent_app_date] => 2001-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4950 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20020180493.pdf [firstpage_image] =>[orig_patent_app_number] => 10012178 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/012178
Bipolar comparator Oct 28, 2001 Issued
Array ( [id] => 1421448 [patent_doc_number] => 06525573 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Signal processing architecture' [patent_app_type] => B1 [patent_app_number] => 10/039762 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4683 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525573.pdf [firstpage_image] =>[orig_patent_app_number] => 10039762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039762
Signal processing architecture Oct 25, 2001 Issued
Array ( [id] => 1338412 [patent_doc_number] => 06597230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Electronic device' [patent_app_type] => B2 [patent_app_number] => 10/144824 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3491 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597230.pdf [firstpage_image] =>[orig_patent_app_number] => 10144824 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144824
Electronic device Oct 24, 2001 Issued
Array ( [id] => 5933921 [patent_doc_number] => 20020060561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Voltage level detector and voltage generator using the same' [patent_app_type] => new [patent_app_number] => 09/981964 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4904 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060561.pdf [firstpage_image] =>[orig_patent_app_number] => 09981964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981964
Voltage level detector and voltage generator using the same Oct 18, 2001 Issued
Array ( [id] => 6480015 [patent_doc_number] => 20020024365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Gate coupled voltage support for an output driver circuit' [patent_app_type] => new [patent_app_number] => 09/977661 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4632 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024365.pdf [firstpage_image] =>[orig_patent_app_number] => 09977661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977661
Gate coupled voltage support for an output driver circuit Oct 14, 2001 Issued
Array ( [id] => 1537053 [patent_doc_number] => 06489817 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Clock divider using positive and negative edge triggered state machines' [patent_app_type] => B1 [patent_app_number] => 09/965290 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4815 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489817.pdf [firstpage_image] =>[orig_patent_app_number] => 09965290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965290
Clock divider using positive and negative edge triggered state machines Sep 25, 2001 Issued
Array ( [id] => 1452948 [patent_doc_number] => 06456125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Distributed high frequency circuit equipped with bias bypass line to reduce chip area' [patent_app_type] => B1 [patent_app_number] => 09/956926 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5833 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456125.pdf [firstpage_image] =>[orig_patent_app_number] => 09956926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956926
Distributed high frequency circuit equipped with bias bypass line to reduce chip area Sep 20, 2001 Issued
Array ( [id] => 1419710 [patent_doc_number] => 06529064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method and device for controlling an electrical load' [patent_app_type] => B2 [patent_app_number] => 09/953355 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529064.pdf [firstpage_image] =>[orig_patent_app_number] => 09953355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953355
Method and device for controlling an electrical load Sep 16, 2001 Issued
Array ( [id] => 5871751 [patent_doc_number] => 20020047732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Peak-hold circuit with variable time constant' [patent_app_type] => new [patent_app_number] => 09/951222 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11791 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047732.pdf [firstpage_image] =>[orig_patent_app_number] => 09951222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951222
Peak-hold circuit with variable time constant Sep 13, 2001 Abandoned
Array ( [id] => 1215496 [patent_doc_number] => RE038455 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Controllable integrator' [patent_app_type] => E1 [patent_app_number] => 09/950086 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1380 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038455.pdf [firstpage_image] =>[orig_patent_app_number] => 09950086 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950086
Controllable integrator Sep 11, 2001 Issued
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