
Toan V. Tran
Examiner (ID: 4400)
| Most Active Art Unit | 2816 |
| Art Unit(s) | 2899, 2816, 2504, 3621 |
| Total Applications | 1179 |
| Issued Applications | 1083 |
| Pending Applications | 23 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1588566
[patent_doc_number] => 06359478
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor'
[patent_app_type] => B1
[patent_app_number] => 09/682437
[patent_app_country] => US
[patent_app_date] => 2001-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2681
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/359/06359478.pdf
[firstpage_image] =>[orig_patent_app_number] => 09682437
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/682437 | Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor | Aug 30, 2001 | Issued |
Array
(
[id] => 6480208
[patent_doc_number] => 20020024374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-28
[patent_title] => 'Circuit and method for an integrated level shifting latch'
[patent_app_type] => new
[patent_app_number] => 09/940957
[patent_app_country] => US
[patent_app_date] => 2001-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4275
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20020024374.pdf
[firstpage_image] =>[orig_patent_app_number] => 09940957
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/940957 | Circuit and method for an integrated level shifting latch | Aug 26, 2001 | Abandoned |
Array
(
[id] => 5919002
[patent_doc_number] => 20020113769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'Level shift circuit and semiconductor device using the same'
[patent_app_type] => new
[patent_app_number] => 09/930884
[patent_app_country] => US
[patent_app_date] => 2001-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6014
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20020113769.pdf
[firstpage_image] =>[orig_patent_app_number] => 09930884
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/930884 | Level shift circuit and semiconductor device using the same | Aug 13, 2001 | Issued |
Array
(
[id] => 7646873
[patent_doc_number] => 06476645
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit'
[patent_app_type] => B1
[patent_app_number] => 09/927673
[patent_app_country] => US
[patent_app_date] => 2001-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4188
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/476/06476645.pdf
[firstpage_image] =>[orig_patent_app_number] => 09927673
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/927673 | Method and apparatus for mitigating the history effect in a silicon-on-insulator (SOI)-based circuit | Aug 9, 2001 | Issued |
Array
(
[id] => 6029525
[patent_doc_number] => 20020017928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-14
[patent_title] => 'Comparator circuit'
[patent_app_type] => new
[patent_app_number] => 09/925167
[patent_app_country] => US
[patent_app_date] => 2001-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4740
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 328
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20020017928.pdf
[firstpage_image] =>[orig_patent_app_number] => 09925167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/925167 | Comparator circuit | Aug 7, 2001 | Issued |
Array
(
[id] => 1413650
[patent_doc_number] => 06535050
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-03-18
[patent_title] => 'Hybrid power MOSFET for high current-carrying capacity'
[patent_app_type] => B2
[patent_app_number] => 09/911167
[patent_app_country] => US
[patent_app_date] => 2001-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1716
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535050.pdf
[firstpage_image] =>[orig_patent_app_number] => 09911167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/911167 | Hybrid power MOSFET for high current-carrying capacity | Jul 22, 2001 | Issued |
Array
(
[id] => 5886375
[patent_doc_number] => 20020011876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-31
[patent_title] => 'Current sense amplifiers enabling amplification of bit line voltages provided by bit line sense amplifiers'
[patent_app_type] => new
[patent_app_number] => 09/903128
[patent_app_country] => US
[patent_app_date] => 2001-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4371
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20020011876.pdf
[firstpage_image] =>[orig_patent_app_number] => 09903128
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/903128 | Current sense amplifiers enabling amplification of bit line voltages provided by bit line sense amplifiers | Jul 10, 2001 | Issued |
Array
(
[id] => 6335373
[patent_doc_number] => 20020033714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'Digital phase detector circuit and method therefor'
[patent_app_type] => new
[patent_app_number] => 09/902542
[patent_app_country] => US
[patent_app_date] => 2001-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12977
[patent_no_of_claims] => 63
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20020033714.pdf
[firstpage_image] =>[orig_patent_app_number] => 09902542
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/902542 | Digital phase detector circuit and method therefor | Jul 9, 2001 | Issued |
Array
(
[id] => 1452939
[patent_doc_number] => 06456122
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Input buffer circuit for transforming pseudo differential signals into full differential signals'
[patent_app_type] => B1
[patent_app_number] => 09/899223
[patent_app_country] => US
[patent_app_date] => 2001-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2005
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/456/06456122.pdf
[firstpage_image] =>[orig_patent_app_number] => 09899223
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/899223 | Input buffer circuit for transforming pseudo differential signals into full differential signals | Jul 5, 2001 | Issued |
Array
(
[id] => 6590791
[patent_doc_number] => 20020015338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'Delay locked loop for use in semiconductor memory device'
[patent_app_type] => new
[patent_app_number] => 09/897829
[patent_app_country] => US
[patent_app_date] => 2001-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6288
[patent_no_of_claims] => 80
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20020015338.pdf
[firstpage_image] =>[orig_patent_app_number] => 09897829
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/897829 | Delay locked loop for use in semiconductor memory device | Jun 28, 2001 | Issued |
Array
(
[id] => 1426112
[patent_doc_number] => 06515531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-04
[patent_title] => 'Multichip configuration'
[patent_app_type] => B2
[patent_app_number] => 09/894679
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3404
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/515/06515531.pdf
[firstpage_image] =>[orig_patent_app_number] => 09894679
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/894679 | Multichip configuration | Jun 27, 2001 | Issued |
Array
(
[id] => 1469061
[patent_doc_number] => 06459307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-01
[patent_title] => 'Input buffer having dual paths'
[patent_app_type] => B2
[patent_app_number] => 09/896437
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2371
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459307.pdf
[firstpage_image] =>[orig_patent_app_number] => 09896437
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/896437 | Input buffer having dual paths | Jun 27, 2001 | Issued |
Array
(
[id] => 1424310
[patent_doc_number] => 06518817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-11
[patent_title] => 'Voltage buffer'
[patent_app_type] => B2
[patent_app_number] => 09/894464
[patent_app_country] => US
[patent_app_date] => 2001-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 26
[patent_no_of_words] => 5794
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518817.pdf
[firstpage_image] =>[orig_patent_app_number] => 09894464
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/894464 | Voltage buffer | Jun 27, 2001 | Issued |
Array
(
[id] => 1424092
[patent_doc_number] => 06518799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-02-11
[patent_title] => 'Comparator and a control circuit for a power MOSFET'
[patent_app_type] => B2
[patent_app_number] => 09/891236
[patent_app_country] => US
[patent_app_date] => 2001-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2682
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/518/06518799.pdf
[firstpage_image] =>[orig_patent_app_number] => 09891236
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/891236 | Comparator and a control circuit for a power MOSFET | Jun 26, 2001 | Issued |
Array
(
[id] => 6461923
[patent_doc_number] => 20020021151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-21
[patent_title] => 'Output buffer circuit'
[patent_app_type] => new
[patent_app_number] => 09/892068
[patent_app_country] => US
[patent_app_date] => 2001-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8834
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0021/20020021151.pdf
[firstpage_image] =>[orig_patent_app_number] => 09892068
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/892068 | Output buffer circuit | Jun 24, 2001 | Issued |
Array
(
[id] => 1441330
[patent_doc_number] => 06496050
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-17
[patent_title] => 'Selective modification of clock pulses'
[patent_app_type] => B2
[patent_app_number] => 09/888043
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2344
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/496/06496050.pdf
[firstpage_image] =>[orig_patent_app_number] => 09888043
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/888043 | Selective modification of clock pulses | Jun 20, 2001 | Issued |
Array
(
[id] => 1413364
[patent_doc_number] => 06535030
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Differential comparator with offset correction'
[patent_app_type] => B1
[patent_app_number] => 09/884725
[patent_app_country] => US
[patent_app_date] => 2001-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3452
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535030.pdf
[firstpage_image] =>[orig_patent_app_number] => 09884725
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/884725 | Differential comparator with offset correction | Jun 18, 2001 | Issued |
Array
(
[id] => 1487420
[patent_doc_number] => 06366147
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-04-02
[patent_title] => 'High performance impulse flip-flops'
[patent_app_type] => B2
[patent_app_number] => 09/874866
[patent_app_country] => US
[patent_app_date] => 2001-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3006
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/366/06366147.pdf
[firstpage_image] =>[orig_patent_app_number] => 09874866
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/874866 | High performance impulse flip-flops | Jun 3, 2001 | Issued |
Array
(
[id] => 6933604
[patent_doc_number] => 20010054948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-12-27
[patent_title] => 'Fuse circuit configuration'
[patent_app_type] => new
[patent_app_number] => 09/867257
[patent_app_country] => US
[patent_app_date] => 2001-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1921
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20010054948.pdf
[firstpage_image] =>[orig_patent_app_number] => 09867257
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/867257 | Fuse circuit configuration | May 28, 2001 | Issued |
Array
(
[id] => 5949049
[patent_doc_number] => 20020005739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-17
[patent_title] => 'Comparing circuit and demodulator circuit using same'
[patent_app_type] => new
[patent_app_number] => 09/860766
[patent_app_country] => US
[patent_app_date] => 2001-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7961
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0005/20020005739.pdf
[firstpage_image] =>[orig_patent_app_number] => 09860766
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/860766 | Comparing circuit and demodulator circuit using same | May 20, 2001 | Issued |