Search

Todd E. Manahan

Supervisory Patent Examiner (ID: 12396, Phone: (571)272-4713 , Office: P/3776 )

Most Active Art Unit
3732
Art Unit(s)
3741, 3776, 3616, 3732, 3731, 3734, 3303
Total Applications
1893
Issued Applications
1366
Pending Applications
210
Abandoned Applications
317

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19775375 [patent_doc_number] => 20250056801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => VERTICAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/929113 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929113
VERTICAL MEMORY DEVICES Oct 27, 2024 Pending
Array ( [id] => 19758158 [patent_doc_number] => 20250046723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/922192 [patent_app_country] => US [patent_app_date] => 2024-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922192 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/922192
SEMICONDUCTOR DIE ASSEMBLIES WITH DECOMPOSABLE MATERIALS AND ASSOCIATED METHODS AND SYSTEMS Oct 20, 2024 Pending
Array ( [id] => 19850800 [patent_doc_number] => 20250096151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING [patent_app_type] => utility [patent_app_number] => 18/788822 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788822 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788822
WIRE BONDING METHOD AND APPARATUS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING Jul 29, 2024 Pending
Array ( [id] => 19951332 [patent_doc_number] => 12322703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Eccentric via structures for stress reduction [patent_app_type] => utility [patent_app_number] => 18/766974 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 1075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766974
Eccentric via structures for stress reduction Jul 8, 2024 Issued
Array ( [id] => 19500390 [patent_doc_number] => 20240339408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Semiconductor Package and Method [patent_app_type] => utility [patent_app_number] => 18/745613 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745613
Semiconductor package and method Jun 16, 2024 Issued
Array ( [id] => 19484169 [patent_doc_number] => 20240332211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/740503 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740503 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740503
Package structure Jun 10, 2024 Issued
Array ( [id] => 19421042 [patent_doc_number] => 20240297166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/664483 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664483 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664483
Integrated circuit package and method of forming same May 14, 2024 Issued
Array ( [id] => 19421015 [patent_doc_number] => 20240297139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/646951 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646951
Semiconductor package Apr 25, 2024 Issued
Array ( [id] => 19384623 [patent_doc_number] => 20240274493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/644068 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644068
Semiconductor device and manufacturing method thereof Apr 22, 2024 Issued
Array ( [id] => 19384629 [patent_doc_number] => 20240274499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/643144 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643144 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643144
Semiconductor package Apr 22, 2024 Issued
Array ( [id] => 19392848 [patent_doc_number] => 20240282718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => INTERPOSER WITH WARPAGE-RELIEF TRENCHES [patent_app_type] => utility [patent_app_number] => 18/628804 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628804
Interposer with warpage-relief trenches Apr 7, 2024 Issued
Array ( [id] => 19321482 [patent_doc_number] => 20240243029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/623010 [patent_app_country] => US [patent_app_date] => 2024-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623010
Semiconductor device structures and methods of manufacturing the same Mar 30, 2024 Issued
Array ( [id] => 19305677 [patent_doc_number] => 20240234257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => SIGNAL ISOLATOR HAVING ENHANCED CREEPAGE CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 18/618259 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618259
Signal isolator having enhanced creepage characteristics Mar 26, 2024 Issued
Array ( [id] => 19285829 [patent_doc_number] => 20240222306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ELECTRONIC PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/610185 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610185 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610185
Electronic package structure and method for manufacturing the same Mar 18, 2024 Issued
Array ( [id] => 19269613 [patent_doc_number] => 20240213317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING PROTRUDING INSULATION PORTIONS BETWEEN ACTIVE FINS [patent_app_type] => utility [patent_app_number] => 18/596461 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596461
Semiconductor devices including protruding insulation portions between active fins Mar 4, 2024 Issued
Array ( [id] => 19972483 [patent_doc_number] => 12341104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Methods of manufacturing semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/442062 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442062
Methods of manufacturing semiconductor devices Feb 13, 2024 Issued
Array ( [id] => 19720373 [patent_doc_number] => 12205916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Honeycomb pattern for conductive features [patent_app_type] => utility [patent_app_number] => 18/436643 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436643
Honeycomb pattern for conductive features Feb 7, 2024 Issued
Array ( [id] => 19161205 [patent_doc_number] => 20240153912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => OVERLAPPING DIE STACKS FOR NAND PACKAGE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/416180 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416180
Overlapping die stacks for NAND package architecture Jan 17, 2024 Issued
Array ( [id] => 19705016 [patent_doc_number] => 12199063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Microelectronic assemblies [patent_app_type] => utility [patent_app_number] => 18/403545 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 57 [patent_no_of_words] => 20914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403545
Microelectronic assemblies Jan 2, 2024 Issued
Array ( [id] => 19957408 [patent_doc_number] => 12327827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Microelectronic assemblies [patent_app_type] => utility [patent_app_number] => 18/397873 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 57 [patent_no_of_words] => 15741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397873
Microelectronic assemblies Dec 26, 2023 Issued
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