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Todd Michael Epps

Examiner (ID: 7875, Phone: (571)272-8282 , Office: P/3632 )

Most Active Art Unit
3632
Art Unit(s)
3632
Total Applications
1419
Issued Applications
980
Pending Applications
70
Abandoned Applications
369

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11049772 [patent_doc_number] => 20160246731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'SELECTIVE TRANSLATION LOOKASIDE BUFFER SEARCH AND PAGE FAULT' [patent_app_type] => utility [patent_app_number] => 14/626925 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7779 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/626925
Selective translation lookaside buffer search and page fault Feb 19, 2015 Issued
Array ( [id] => 11049559 [patent_doc_number] => 20160246518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'RAID ARRAY SYSTEMS AND OPERATIONS USING MAPPING INFORMATION' [patent_app_type] => utility [patent_app_number] => 14/627401 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 18549 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14627401 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/627401
RAID array systems and operations using mapping information Feb 19, 2015 Issued
Array ( [id] => 12039543 [patent_doc_number] => 09817776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Memory descriptor list caching and pipeline processing' [patent_app_type] => utility [patent_app_number] => 14/626681 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626681 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/626681
Memory descriptor list caching and pipeline processing Feb 18, 2015 Issued
Array ( [id] => 10078773 [patent_doc_number] => 09116621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-25 [patent_title] => 'System and method of transfer of control between memory locations' [patent_app_type] => utility [patent_app_number] => 14/596631 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7190 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596631 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/596631
System and method of transfer of control between memory locations Jan 13, 2015 Issued
Array ( [id] => 10536451 [patent_doc_number] => 09262080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Reducing read latency using a pool of processing cores' [patent_app_type] => utility [patent_app_number] => 14/590724 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9239 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590724 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590724
Reducing read latency using a pool of processing cores Jan 5, 2015 Issued
Array ( [id] => 10376438 [patent_doc_number] => 20150261445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'DATA DE-DUPLICATION FOR INFORMATION STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/589218 [patent_app_country] => US [patent_app_date] => 2015-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12970 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14589218 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/589218
Data de-duplication for information storage systems Jan 4, 2015 Issued
Array ( [id] => 10301220 [patent_doc_number] => 20150186220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'INCREASING GRANULARITY OF DIRTY BIT INFORMATION' [patent_app_type] => utility [patent_app_number] => 14/588594 [patent_app_country] => US [patent_app_date] => 2015-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14588594 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/588594
Increasing granularity of dirty bit information Jan 1, 2015 Issued
Array ( [id] => 12392805 [patent_doc_number] => 09965183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Method for processing data in storage device and storage device [patent_app_type] => utility [patent_app_number] => 14/586660 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4565 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14586660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/586660
Method for processing data in storage device and storage device Dec 29, 2014 Issued
Array ( [id] => 10424518 [patent_doc_number] => 20150309529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'MEMORY MIRRORING' [patent_app_type] => utility [patent_app_number] => 14/568848 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14568848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/568848
Memory mirroring Dec 11, 2014 Issued
Array ( [id] => 11220583 [patent_doc_number] => 09448920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Granting and revoking supplemental memory allocation requests' [patent_app_type] => utility [patent_app_number] => 14/559811 [patent_app_country] => US [patent_app_date] => 2014-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5089 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14559811 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/559811
Granting and revoking supplemental memory allocation requests Dec 2, 2014 Issued
Array ( [id] => 9933803 [patent_doc_number] => 20150081995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DATA PROTECTION WITH MULTIPLE SITE REPLICATION' [patent_app_type] => utility [patent_app_number] => 14/551543 [patent_app_country] => US [patent_app_date] => 2014-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14551543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/551543
Data protection with multiple site replication Nov 23, 2014 Issued
Array ( [id] => 11509200 [patent_doc_number] => 09600360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Dynamic partial blocking of a cache ECC bypass' [patent_app_type] => utility [patent_app_number] => 14/549575 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4661 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549575 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/549575
Dynamic partial blocking of a cache ECC bypass Nov 20, 2014 Issued
Array ( [id] => 11732596 [patent_doc_number] => 20170194040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'PROGRAM AND DEVICE FOR SUPPRESSING TEMPERATURE RISE OF MEMORY' [patent_app_type] => utility [patent_app_number] => 15/302092 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5944 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15302092 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/302092
PROGRAM AND DEVICE FOR SUPPRESSING TEMPERATURE RISE OF MEMORY Nov 10, 2014 Abandoned
Array ( [id] => 10739531 [patent_doc_number] => 20160085682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Caching Methodology for Dynamic Semantic Tables' [patent_app_type] => utility [patent_app_number] => 14/521039 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13214 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521039 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521039
Caching Methodology for Dynamic Semantic Tables Oct 21, 2014 Abandoned
Array ( [id] => 10221572 [patent_doc_number] => 20150106566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'Computer Processor Employing Dedicated Hardware Mechanism Controlling The Initialization And Invalidation Of Cache Lines' [patent_app_type] => utility [patent_app_number] => 14/515231 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515231 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515231
Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines Oct 14, 2014 Issued
Array ( [id] => 10221574 [patent_doc_number] => 20150106567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'Computer Processor Employing Cache Memory With Per-Byte Valid Bits' [patent_app_type] => utility [patent_app_number] => 14/515178 [patent_app_country] => US [patent_app_date] => 2014-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15653 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14515178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/515178
Computer processor employing cache memory with per-byte valid bits Oct 14, 2014 Issued
Array ( [id] => 17331303 [patent_doc_number] => 11221764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Partitioned memory with shared memory resources and configurable functions [patent_app_type] => utility [patent_app_number] => 14/503382 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 17001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503382 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503382
Partitioned memory with shared memory resources and configurable functions Sep 29, 2014 Issued
Array ( [id] => 10210555 [patent_doc_number] => 20150095545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD AND APPARATUS FOR CONTROLLING CACHE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/496559 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5842 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496559 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496559
Method and apparatus for controlling cache memory Sep 24, 2014 Issued
Array ( [id] => 10746202 [patent_doc_number] => 20160092353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY' [patent_app_type] => utility [patent_app_number] => 14/496773 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4110 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496773 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496773
ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY Sep 24, 2014 Abandoned
Array ( [id] => 10745987 [patent_doc_number] => 20160092137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Data Integrity In Deduplicated Block Storage Environments' [patent_app_type] => utility [patent_app_number] => 14/496370 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496370 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496370
Data integrity in deduplicated block storage environments Sep 24, 2014 Issued
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