Search

Todd Michael Epps

Examiner (ID: 7875, Phone: (571)272-8282 , Office: P/3632 )

Most Active Art Unit
3632
Art Unit(s)
3632
Total Applications
1419
Issued Applications
980
Pending Applications
70
Abandoned Applications
369

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9992585 [patent_doc_number] => 09037806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Reducing store operation busy times' [patent_app_type] => utility [patent_app_number] => 13/790354 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4776 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790354 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790354
Reducing store operation busy times Mar 7, 2013 Issued
Array ( [id] => 8893652 [patent_doc_number] => 20130166836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'CONFIGURABLE MEMORY CONTROLLER/MEMORY MODULE COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/776295 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776295 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776295
Configurable memory controller/memory module communication system Feb 24, 2013 Issued
Array ( [id] => 9392278 [patent_doc_number] => 08688900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Cache memory management in a flash cache architecture' [patent_app_type] => utility [patent_app_number] => 13/758590 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758590 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758590
Cache memory management in a flash cache architecture Feb 3, 2013 Issued
Array ( [id] => 8965460 [patent_doc_number] => 20130205062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'SYSTEM AND METHOD TO PRIORITIZE LARGE MEMORY PAGE ALLOCATION IN VIRTUALIZED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/753322 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7073 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753322
System and method to prioritize large memory page allocation in virtualized systems Jan 28, 2013 Issued
Array ( [id] => 10439275 [patent_doc_number] => 20150324287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS' [patent_app_type] => utility [patent_app_number] => 14/655109 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14655109 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/655109
A METHOD AND APPARATUS FOR USING A CPU CACHE MEMORY FOR NON-CPU RELATED TASKS Jan 8, 2013 Abandoned
Array ( [id] => 8978888 [patent_doc_number] => 20130212318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/725671 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5721 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725671 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725671
Architecture for address mapping of managed non-volatile memory Dec 20, 2012 Issued
Array ( [id] => 9548570 [patent_doc_number] => 20140173219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'LIGHTWEIGHT OBSERVABLE VALUES FOR MULTIPLE GRIDS' [patent_app_type] => utility [patent_app_number] => 13/719622 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719622 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719622
Lightweight observable values for multiple grids Dec 18, 2012 Issued
Array ( [id] => 9548552 [patent_doc_number] => 20140173200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'NON-BLOCKING CACHING TECHNIQUE' [patent_app_type] => utility [patent_app_number] => 13/719252 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13719252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/719252
Non-blocking caching technique Dec 18, 2012 Issued
Array ( [id] => 9320574 [patent_doc_number] => 20140052912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'MEMORY DEVICE WITH A LOGICAL-TO-PHYSICAL BANK MAPPING CACHE' [patent_app_type] => utility [patent_app_number] => 13/718773 [patent_app_country] => US [patent_app_date] => 2012-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13718773 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/718773
Memory device with a logical-to-physical bank mapping cache Dec 17, 2012 Issued
Array ( [id] => 9049205 [patent_doc_number] => 08543763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Redundant array of independent disks raid controller and system' [patent_app_type] => utility [patent_app_number] => 13/715534 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4563 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715534 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715534
Redundant array of independent disks raid controller and system Dec 13, 2012 Issued
Array ( [id] => 10124338 [patent_doc_number] => 09158697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Method for cleaning cache of processor and associated processor' [patent_app_type] => utility [patent_app_number] => 13/691841 [patent_app_country] => US [patent_app_date] => 2012-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1664 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691841 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691841
Method for cleaning cache of processor and associated processor Dec 1, 2012 Issued
Array ( [id] => 9974168 [patent_doc_number] => 09021205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Page replacement in cache memory' [patent_app_type] => utility [patent_app_number] => 13/690191 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/690191
Page replacement in cache memory Nov 29, 2012 Issued
Array ( [id] => 10369170 [patent_doc_number] => 20150254175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'MEMORY MODULE INCLUDING MEMORY RESISTORS' [patent_app_type] => utility [patent_app_number] => 14/432245 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14432245 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/432245
Memory module including memory resistors Nov 28, 2012 Issued
Array ( [id] => 10034393 [patent_doc_number] => 09075712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Scheduling requests in a solid state memory device' [patent_app_type] => utility [patent_app_number] => 13/688270 [patent_app_country] => US [patent_app_date] => 2012-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8671 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13688270 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/688270
Scheduling requests in a solid state memory device Nov 28, 2012 Issued
Array ( [id] => 9513147 [patent_doc_number] => 20140149639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 13/687147 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687147 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/687147
Coding techniques for reducing write cycles for memory Nov 27, 2012 Issued
Array ( [id] => 9940652 [patent_doc_number] => 08990483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Nonvolatile memory device, memory system, and program method therof' [patent_app_type] => utility [patent_app_number] => 13/685772 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 15014 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685772
Nonvolatile memory device, memory system, and program method therof Nov 26, 2012 Issued
Array ( [id] => 9940701 [patent_doc_number] => 08990533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-24 [patent_title] => 'Crash consistency' [patent_app_type] => utility [patent_app_number] => 13/684953 [patent_app_country] => US [patent_app_date] => 2012-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13684953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/684953
Crash consistency Nov 25, 2012 Issued
Array ( [id] => 9458510 [patent_doc_number] => 08719535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Method and system for non-disruptive migration' [patent_app_type] => utility [patent_app_number] => 13/673035 [patent_app_country] => US [patent_app_date] => 2012-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 12258 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13673035 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/673035
Method and system for non-disruptive migration Nov 8, 2012 Issued
Array ( [id] => 9527441 [patent_doc_number] => 08751733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Hybrid memory management' [patent_app_type] => utility [patent_app_number] => 13/657392 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6917 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657392
Hybrid memory management Oct 21, 2012 Issued
Array ( [id] => 9424075 [patent_doc_number] => 20140108727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'STORAGE APPARATUS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/643440 [patent_app_country] => US [patent_app_date] => 2012-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14155 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13643440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/643440
Storage apparatus and data processing method Oct 10, 2012 Issued
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