| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3093760
[patent_doc_number] => 05298447
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Method of fabricating a flash memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/094744
[patent_app_country] => US
[patent_app_date] => 1993-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2196
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/298/05298447.pdf
[firstpage_image] =>[orig_patent_app_number] => 094744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/094744 | Method of fabricating a flash memory cell | Jul 21, 1993 | Issued |
Array
(
[id] => 3408514
[patent_doc_number] => 05393233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Process for fabricating double poly high density buried bit line mask ROM'
[patent_app_type] => 1
[patent_app_number] => 8/092190
[patent_app_country] => US
[patent_app_date] => 1993-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 1750
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/393/05393233.pdf
[firstpage_image] =>[orig_patent_app_number] => 092190
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/092190 | Process for fabricating double poly high density buried bit line mask ROM | Jul 13, 1993 | Issued |
Array
(
[id] => 2999722
[patent_doc_number] => 05371031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions'
[patent_app_type] => 1
[patent_app_number] => 8/089206
[patent_app_country] => US
[patent_app_date] => 1993-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6555
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371031.pdf
[firstpage_image] =>[orig_patent_app_number] => 089206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089206 | Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions | Jul 8, 1993 | Issued |
| 08/088312 | DIELECTRIC STRUCTURE FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING SAME | Jul 6, 1993 | Pending |
Array
(
[id] => 3006552
[patent_doc_number] => 05354702
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Electrical erasable and programmable read-only memory and manufacturing method therefor'
[patent_app_type] => 1
[patent_app_number] => 8/084092
[patent_app_country] => US
[patent_app_date] => 1993-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2408
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/354/05354702.pdf
[firstpage_image] =>[orig_patent_app_number] => 084092
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/084092 | Electrical erasable and programmable read-only memory and manufacturing method therefor | Jun 30, 1993 | Issued |
Array
(
[id] => 3071590
[patent_doc_number] => 05364812
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'High density dynamic RAM cell'
[patent_app_type] => 1
[patent_app_number] => 8/086524
[patent_app_country] => US
[patent_app_date] => 1993-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3045
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/364/05364812.pdf
[firstpage_image] =>[orig_patent_app_number] => 086524
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086524 | High density dynamic RAM cell | Jun 30, 1993 | Issued |
Array
(
[id] => 2989225
[patent_doc_number] => 05346846
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Method of manufacturing a highly integrated semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/084760
[patent_app_country] => US
[patent_app_date] => 1993-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1390
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 290
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/346/05346846.pdf
[firstpage_image] =>[orig_patent_app_number] => 084760
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/084760 | Method of manufacturing a highly integrated semiconductor device | Jun 28, 1993 | Issued |
Array
(
[id] => 3006574
[patent_doc_number] => 05354703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'EEPROM cell array with tight erase distribution'
[patent_app_type] => 1
[patent_app_number] => 8/085430
[patent_app_country] => US
[patent_app_date] => 1993-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4904
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/354/05354703.pdf
[firstpage_image] =>[orig_patent_app_number] => 085430
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/085430 | EEPROM cell array with tight erase distribution | Jun 28, 1993 | Issued |
Array
(
[id] => 3107140
[patent_doc_number] => 05407852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Method of making NOR-type ROM with LDD cells'
[patent_app_type] => 1
[patent_app_number] => 8/084971
[patent_app_country] => US
[patent_app_date] => 1993-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 14
[patent_no_of_words] => 4963
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/407/05407852.pdf
[firstpage_image] =>[orig_patent_app_number] => 084971
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/084971 | Method of making NOR-type ROM with LDD cells | Jun 27, 1993 | Issued |
Array
(
[id] => 3057353
[patent_doc_number] => 05350710
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Device for preventing antenna effect on circuit'
[patent_app_type] => 1
[patent_app_number] => 8/080536
[patent_app_country] => US
[patent_app_date] => 1993-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1818
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/350/05350710.pdf
[firstpage_image] =>[orig_patent_app_number] => 080536
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/080536 | Device for preventing antenna effect on circuit | Jun 23, 1993 | Issued |
Array
(
[id] => 3012283
[patent_doc_number] => 05332685
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Method of manufacturing a DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 8/082276
[patent_app_country] => US
[patent_app_date] => 1993-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1678
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/332/05332685.pdf
[firstpage_image] =>[orig_patent_app_number] => 082276
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/082276 | Method of manufacturing a DRAM cell | Jun 23, 1993 | Issued |
| 08/083120 | METHOD FOR FORMING A CAPACITOR OF A SEMICONDUCTOR MEMORY CELL | Jun 23, 1993 | Pending |
Array
(
[id] => 3539398
[patent_doc_number] => 05480824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Semiconductor memory cell capacitor and fabrication method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/079186
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 22
[patent_no_of_words] => 2662
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 354
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/480/05480824.pdf
[firstpage_image] =>[orig_patent_app_number] => 079186
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/079186 | Semiconductor memory cell capacitor and fabrication method thereof | Jun 17, 1993 | Issued |
Array
(
[id] => 3057318
[patent_doc_number] => 05350708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-27
[patent_title] => 'Method of making dynamic random access semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/077744
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 41
[patent_no_of_words] => 5685
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/350/05350708.pdf
[firstpage_image] =>[orig_patent_app_number] => 077744
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077744 | Method of making dynamic random access semiconductor memory device | Jun 17, 1993 | Issued |
Array
(
[id] => 3006800
[patent_doc_number] => 05330938
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation'
[patent_app_type] => 1
[patent_app_number] => 8/077934
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 33
[patent_no_of_words] => 2541
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/330/05330938.pdf
[firstpage_image] =>[orig_patent_app_number] => 077934
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077934 | Method of making non-volatile split gate EPROM memory cell and self-aligned field insulation | Jun 17, 1993 | Issued |
Array
(
[id] => 3068568
[patent_doc_number] => 05322438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Layout scheme for precise capacitance ratios'
[patent_app_type] => 1
[patent_app_number] => 8/079646
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3814
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/322/05322438.pdf
[firstpage_image] =>[orig_patent_app_number] => 079646
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/079646 | Layout scheme for precise capacitance ratios | Jun 17, 1993 | Issued |
Array
(
[id] => 3444775
[patent_doc_number] => 05397745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Method of making electronic power device realized by a series of elementary semiconductor components connected in parallel'
[patent_app_type] => 1
[patent_app_number] => 8/077375
[patent_app_country] => US
[patent_app_date] => 1993-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2444
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397745.pdf
[firstpage_image] =>[orig_patent_app_number] => 077375
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077375 | Method of making electronic power device realized by a series of elementary semiconductor components connected in parallel | Jun 16, 1993 | Issued |
Array
(
[id] => 3460846
[patent_doc_number] => 05468661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Method of making power VFET device'
[patent_app_type] => 1
[patent_app_number] => 8/078388
[patent_app_country] => US
[patent_app_date] => 1993-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 17
[patent_no_of_words] => 3044
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/468/05468661.pdf
[firstpage_image] =>[orig_patent_app_number] => 078388
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/078388 | Method of making power VFET device | Jun 16, 1993 | Issued |
| 08/075912 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING ISOLATION OXIDE REGIONS WITH DIFFERENT THICKNESS | Jun 13, 1993 | Pending |
Array
(
[id] => 3004403
[patent_doc_number] => 05374571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-20
[patent_title] => 'Vertical power MOS device with increased ruggedness and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/072802
[patent_app_country] => US
[patent_app_date] => 1993-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5138
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/374/05374571.pdf
[firstpage_image] =>[orig_patent_app_number] => 072802
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/072802 | Vertical power MOS device with increased ruggedness and method of fabrication | Jun 6, 1993 | Issued |