Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
08/042669 SIMPLIFIED METHOD OF MAKING ACTIVE MATRIX LIQUID CRYSTAL DISPLAY Apr 4, 1993 Issued
08/040695 METHOD OF DEFECT DETERMINATION AND DEFECT ENGINEERING ON PRODUCT WAFERS OF ADVANCED SUBMICRON TECHNOLOGIES Mar 30, 1993 Pending
Array ( [id] => 3027540 [patent_doc_number] => 05316963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/036726 [patent_app_country] => US [patent_app_date] => 1993-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2701 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/316/05316963.pdf [firstpage_image] =>[orig_patent_app_number] => 036726 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/036726
Method for producing semiconductor device Mar 24, 1993 Issued
Array ( [id] => 3049621 [patent_doc_number] => 05306657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Process for forming an FET read only memory device' [patent_app_type] => 1 [patent_app_number] => 8/035182 [patent_app_country] => US [patent_app_date] => 1993-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2036 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/306/05306657.pdf [firstpage_image] =>[orig_patent_app_number] => 035182 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035182
Process for forming an FET read only memory device Mar 21, 1993 Issued
Array ( [id] => 2890507 [patent_doc_number] => 05270243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Dram peripheral circuit contact aspect ratio improvement process' [patent_app_type] => 1 [patent_app_number] => 8/035232 [patent_app_country] => US [patent_app_date] => 1993-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2857 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270243.pdf [firstpage_image] =>[orig_patent_app_number] => 035232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/035232
Dram peripheral circuit contact aspect ratio improvement process Mar 21, 1993 Issued
Array ( [id] => 3474440 [patent_doc_number] => 05427967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Technique for making memory cells in a way which suppresses electrically conductive stringers' [patent_app_type] => 1 [patent_app_number] => 8/031373 [patent_app_country] => US [patent_app_date] => 1993-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2727 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/427/05427967.pdf [firstpage_image] =>[orig_patent_app_number] => 031373 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/031373
Technique for making memory cells in a way which suppresses electrically conductive stringers Mar 10, 1993 Issued
Array ( [id] => 3045624 [patent_doc_number] => 05304506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'On chip decoupling capacitor' [patent_app_type] => 1 [patent_app_number] => 8/029088 [patent_app_country] => US [patent_app_date] => 1993-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1104 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304506.pdf [firstpage_image] =>[orig_patent_app_number] => 029088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/029088
On chip decoupling capacitor Mar 9, 1993 Issued
Array ( [id] => 3029286 [patent_doc_number] => 05342801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Controllable isotropic plasma etching technique for the suppression of stringers in memory cells' [patent_app_type] => 1 [patent_app_number] => 8/028026 [patent_app_country] => US [patent_app_date] => 1993-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4263 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/342/05342801.pdf [firstpage_image] =>[orig_patent_app_number] => 028026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/028026
Controllable isotropic plasma etching technique for the suppression of stringers in memory cells Mar 7, 1993 Issued
Array ( [id] => 3073834 [patent_doc_number] => 05296407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Method of manufacturing a contact structure for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/039604 [patent_app_country] => US [patent_app_date] => 1993-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2674 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296407.pdf [firstpage_image] =>[orig_patent_app_number] => 039604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/039604
Method of manufacturing a contact structure for integrated circuits Mar 4, 1993 Issued
Array ( [id] => 3026986 [patent_doc_number] => 05348906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/026098 [patent_app_country] => US [patent_app_date] => 1993-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4439 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/348/05348906.pdf [firstpage_image] =>[orig_patent_app_number] => 026098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/026098
Method for manufacturing semiconductor device Mar 3, 1993 Issued
Array ( [id] => 2893522 [patent_doc_number] => 05272103 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-21 [patent_title] => 'DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 8/022221 [patent_app_country] => US [patent_app_date] => 1993-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 4393 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/272/05272103.pdf [firstpage_image] =>[orig_patent_app_number] => 022221 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/022221
DRAM having a large dielectric breakdown voltage between an adjacent conductive layer and a capacitor electrode and method of manufacture thereof Feb 24, 1993 Issued
Array ( [id] => 3017273 [patent_doc_number] => 05302541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Manufacturing method of a semiconductor device with a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 8/017904 [patent_app_country] => US [patent_app_date] => 1993-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3739 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/302/05302541.pdf [firstpage_image] =>[orig_patent_app_number] => 017904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/017904
Manufacturing method of a semiconductor device with a trench capacitor Feb 15, 1993 Issued
Array ( [id] => 3043386 [patent_doc_number] => 05286668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Process of fabricating a high capacitance storage node' [patent_app_type] => 1 [patent_app_number] => 8/013064 [patent_app_country] => US [patent_app_date] => 1993-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3656 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/286/05286668.pdf [firstpage_image] =>[orig_patent_app_number] => 013064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/013064
Process of fabricating a high capacitance storage node Feb 2, 1993 Issued
Array ( [id] => 2999706 [patent_doc_number] => 05371030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Method of fabricating field oxide isolation for a contactless flash EPROM cell array' [patent_app_type] => 1 [patent_app_number] => 8/009330 [patent_app_country] => US [patent_app_date] => 1993-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2154 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 462 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371030.pdf [firstpage_image] =>[orig_patent_app_number] => 009330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/009330
Method of fabricating field oxide isolation for a contactless flash EPROM cell array Jan 25, 1993 Issued
Array ( [id] => 3415425 [patent_doc_number] => 05393690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Method of making semiconductor having improved interlevel conductor insulation' [patent_app_type] => 1 [patent_app_number] => 8/006864 [patent_app_country] => US [patent_app_date] => 1993-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 7046 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393690.pdf [firstpage_image] =>[orig_patent_app_number] => 006864 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/006864
Method of making semiconductor having improved interlevel conductor insulation Jan 20, 1993 Issued
Array ( [id] => 3026917 [patent_doc_number] => 05348902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method of designing cells applicable to different design automation systems' [patent_app_type] => 1 [patent_app_number] => 8/005998 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/348/05348902.pdf [firstpage_image] =>[orig_patent_app_number] => 005998 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/005998
Method of designing cells applicable to different design automation systems Jan 18, 1993 Issued
Array ( [id] => 3013044 [patent_doc_number] => 05308778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Method of formation of transistor and logic gates' [patent_app_type] => 1 [patent_app_number] => 8/003813 [patent_app_country] => US [patent_app_date] => 1993-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 11242 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/308/05308778.pdf [firstpage_image] =>[orig_patent_app_number] => 003813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/003813
Method of formation of transistor and logic gates Jan 10, 1993 Issued
08/000440 DOUBLE POLY PROCESS WITH INDEPENDENTLY ADJUSTABLE INTERPOLY DIELECTRIC THICKNESS Jan 3, 1993 Abandoned
Array ( [id] => 3426909 [patent_doc_number] => 05403767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Methods for manufacturing a storage electrode of DRAM cells' [patent_app_type] => 1 [patent_app_number] => 7/998512 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2064 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 545 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/403/05403767.pdf [firstpage_image] =>[orig_patent_app_number] => 998512 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998512
Methods for manufacturing a storage electrode of DRAM cells Dec 29, 1992 Issued
Array ( [id] => 3026950 [patent_doc_number] => 05348904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Method of fabricating semiconductor memory device including an improved substrate structure' [patent_app_type] => 1 [patent_app_number] => 7/993382 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 11782 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/348/05348904.pdf [firstpage_image] =>[orig_patent_app_number] => 993382 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993382
Method of fabricating semiconductor memory device including an improved substrate structure Dec 17, 1992 Issued
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