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Tom Thomas

Supervisory Patent Examiner (ID: 139, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
2899, 1104, 2893, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3013153 [patent_doc_number] => 05308783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Process for the manufacture of a high density cell array of gain memory cells' [patent_app_type] => 1 [patent_app_number] => 7/991776 [patent_app_country] => US [patent_app_date] => 1992-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1849 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/308/05308783.pdf [firstpage_image] =>[orig_patent_app_number] => 991776 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991776
Process for the manufacture of a high density cell array of gain memory cells Dec 15, 1992 Issued
07/990763 METHOD OF MAKING A MEMORY DEVICE WITH PERIPHERAL CIRCUIT Dec 14, 1992 Abandoned
Array ( [id] => 3073697 [patent_doc_number] => 05296400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Method of manufacturing a contact of a highly integrated semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/989196 [patent_app_country] => US [patent_app_date] => 1992-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2682 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296400.pdf [firstpage_image] =>[orig_patent_app_number] => 989196 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/989196
Method of manufacturing a contact of a highly integrated semiconductor device Dec 10, 1992 Issued
Array ( [id] => 3007172 [patent_doc_number] => 05354734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Method for manufacturing an artificial grain boundary type Josephson junction device' [patent_app_type] => 1 [patent_app_number] => 7/986493 [patent_app_country] => US [patent_app_date] => 1992-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3335 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/354/05354734.pdf [firstpage_image] =>[orig_patent_app_number] => 986493 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/986493
Method for manufacturing an artificial grain boundary type Josephson junction device Dec 6, 1992 Issued
Array ( [id] => 2890267 [patent_doc_number] => 05270231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method of manufacturing device having ferroelectric film' [patent_app_type] => 1 [patent_app_number] => 7/984110 [patent_app_country] => US [patent_app_date] => 1992-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2950 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270231.pdf [firstpage_image] =>[orig_patent_app_number] => 984110 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/984110
Method of manufacturing device having ferroelectric film Nov 30, 1992 Issued
Array ( [id] => 2985264 [patent_doc_number] => 05266513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-30 [patent_title] => 'Method of making stacked W-cell capacitor' [patent_app_type] => 1 [patent_app_number] => 7/978595 [patent_app_country] => US [patent_app_date] => 1992-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2470 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/266/05266513.pdf [firstpage_image] =>[orig_patent_app_number] => 978595 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/978595
Method of making stacked W-cell capacitor Nov 18, 1992 Issued
Array ( [id] => 2935167 [patent_doc_number] => 05260228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Method of making a semiconductor device having a charge transfer device, MOSFETs, and bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/977836 [patent_app_country] => US [patent_app_date] => 1992-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260228.pdf [firstpage_image] =>[orig_patent_app_number] => 977836 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/977836
Method of making a semiconductor device having a charge transfer device, MOSFETs, and bipolar transistors Nov 16, 1992 Issued
07/976796 TIGHT CONTROL OF RESISTOR VALUES IN A SRAM PROCESS Nov 15, 1992 Abandoned
Array ( [id] => 3070345 [patent_doc_number] => 05336630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Method of making semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/975884 [patent_app_country] => US [patent_app_date] => 1992-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 3712 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/336/05336630.pdf [firstpage_image] =>[orig_patent_app_number] => 975884 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975884
Method of making semiconductor memory device Nov 12, 1992 Issued
Array ( [id] => 3029269 [patent_doc_number] => 05342800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-30 [patent_title] => 'Method of making memory cell capacitor' [patent_app_type] => 1 [patent_app_number] => 7/975232 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1644 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/342/05342800.pdf [firstpage_image] =>[orig_patent_app_number] => 975232 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975232
Method of making memory cell capacitor Nov 11, 1992 Issued
Array ( [id] => 3443253 [patent_doc_number] => RE035094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Fabrication process for programmable and erasable MOS memory device' [patent_app_type] => 2 [patent_app_number] => 7/974262 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 27 [patent_no_of_words] => 3481 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035094.pdf [firstpage_image] =>[orig_patent_app_number] => 974262 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/974262
Fabrication process for programmable and erasable MOS memory device Nov 9, 1992 Issued
Array ( [id] => 2890471 [patent_doc_number] => 05270241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing' [patent_app_type] => 1 [patent_app_number] => 7/973092 [patent_app_country] => US [patent_app_date] => 1992-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2696 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270241.pdf [firstpage_image] =>[orig_patent_app_number] => 973092 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/973092
Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing Nov 5, 1992 Issued
Array ( [id] => 3098100 [patent_doc_number] => 05314835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/972914 [patent_app_country] => US [patent_app_date] => 1992-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5234 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/314/05314835.pdf [firstpage_image] =>[orig_patent_app_number] => 972914 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/972914
Semiconductor memory device Nov 5, 1992 Issued
Array ( [id] => 3009605 [patent_doc_number] => 05281558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Cloning method and system for hierarchical compaction' [patent_app_type] => 1 [patent_app_number] => 7/970640 [patent_app_country] => US [patent_app_date] => 1992-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5459 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281558.pdf [firstpage_image] =>[orig_patent_app_number] => 970640 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/970640
Cloning method and system for hierarchical compaction Nov 1, 1992 Issued
Array ( [id] => 3013137 [patent_doc_number] => 05308782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Semiconductor memory device and method of formation' [patent_app_type] => 1 [patent_app_number] => 7/966643 [patent_app_country] => US [patent_app_date] => 1992-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 8716 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/308/05308782.pdf [firstpage_image] =>[orig_patent_app_number] => 966643 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966643
Semiconductor memory device and method of formation Oct 25, 1992 Issued
07/965942 MANUFACTURING PROCESS FOR A MONOLITHIC SEMICONDUCTOR DEVICE COMPRISING AT LEAST ONE TRANSISTOR OF AN INTEGRATED CONTROL CIRCUIT AND ONE POWER TRANSISTOR INTEGRATED ON THE SAME CHIP Oct 22, 1992 Abandoned
Array ( [id] => 3091714 [patent_doc_number] => 05290728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/964146 [patent_app_country] => US [patent_app_date] => 1992-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2836 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290728.pdf [firstpage_image] =>[orig_patent_app_number] => 964146 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964146
Method for producing a semiconductor device Oct 18, 1992 Issued
Array ( [id] => 2993188 [patent_doc_number] => 05366906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Wafer level integration and testing' [patent_app_type] => 1 [patent_app_number] => 7/962000 [patent_app_country] => US [patent_app_date] => 1992-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/366/05366906.pdf [firstpage_image] =>[orig_patent_app_number] => 962000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/962000
Wafer level integration and testing Oct 15, 1992 Issued
07/960328 CONTACT-FREE FLOATING-GATE MEMORY ARRAY WITH SILICIDED BURIED BITLINES AND WITH SINGLE-STEP-DEFINED FLOATING GATES Oct 12, 1992 Abandoned
Array ( [id] => 2930227 [patent_doc_number] => 05219781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Method for manufacturing semiconductor memory device having a stacked type capacitor' [patent_app_type] => 1 [patent_app_number] => 7/959572 [patent_app_country] => US [patent_app_date] => 1992-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4260 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219781.pdf [firstpage_image] =>[orig_patent_app_number] => 959572 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/959572
Method for manufacturing semiconductor memory device having a stacked type capacitor Oct 12, 1992 Issued
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