Tom Thomas

Array ( [id] => 3073624 [patent_doc_number] => 05296396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Matrix of EPROM memory cells with a tablecloth structure having an improved capacitative ratio and a process for its manufacture' [patent_app_type] => 1 [patent_app_number] => 7/929418 [patent_app_country] => US [patent_app_date] => 1992-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2144 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296396.pdf [firstpage_image] =>[orig_patent_app_number] => 929418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2932889 [patent_doc_number] => 05229314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation' [patent_app_type] => 1 [patent_app_number] => 7/925153 [patent_app_country] => US [patent_app_date] => 1992-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4639 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229314.pdf [firstpage_image] =>[orig_patent_app_number] => 925153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2893239 [patent_doc_number] => 05240872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions' [patent_app_type] => 1 [patent_app_number] => 7/925148 [patent_app_country] => US [patent_app_date] => 1992-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 46 [patent_no_of_words] => 4966 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/240/05240872.pdf [firstpage_image] =>[orig_patent_app_number] => 925148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2974974 [patent_doc_number] => 05256587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Methods of patterning and manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/911594 [patent_app_country] => US [patent_app_date] => 1992-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 53 [patent_no_of_words] => 5196 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/256/05256587.pdf [firstpage_image] =>[orig_patent_app_number] => 911594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2903356 [patent_doc_number] => 05248629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Process for fabricating capacitor for semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 7/911118 [patent_app_country] => US [patent_app_date] => 1992-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2364 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/248/05248629.pdf [firstpage_image] =>[orig_patent_app_number] => 911118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2940873 [patent_doc_number] => 05223442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Method of making a semiconductor device of a high withstand voltage' [patent_app_type] => 1 [patent_app_number] => 7/911293 [patent_app_country] => US [patent_app_date] => 1992-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 39 [patent_no_of_words] => 6334 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/223/05223442.pdf [firstpage_image] =>[orig_patent_app_number] => 911293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3043829 [patent_doc_number] => 05334547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Method of manufacturing a semiconductor memory having an increased cell capacitance in a restricted cell area' [patent_app_type] => 1 [patent_app_number] => 7/911348 [patent_app_country] => US [patent_app_date] => 1992-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2853 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 671 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/334/05334547.pdf [firstpage_image] =>[orig_patent_app_number] => 911348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3083397 [patent_doc_number] => 05279983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-18 [patent_title] => 'Method of making a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/906376 [patent_app_country] => US [patent_app_date] => 1992-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3105 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/279/05279983.pdf [firstpage_image] =>[orig_patent_app_number] => 906376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2909436 [patent_doc_number] => 05227323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method of manufacturing capacitor elements in an integrated circuit having a compound semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 7/901296 [patent_app_country] => US [patent_app_date] => 1992-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3280 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227323.pdf [firstpage_image] =>[orig_patent_app_number] => 901296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3049104 [patent_doc_number] => 05324676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Method for forming a dual thickness dielectric floating gate memory cell' [patent_app_type] => 1 [patent_app_number] => 7/900894 [patent_app_country] => US [patent_app_date] => 1992-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4196 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324676.pdf [firstpage_image] =>[orig_patent_app_number] => 900894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2967559 [patent_doc_number] => 05258321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Manufacturing method for semiconductor memory device having stacked trench capacitors and improved intercell isolation' [patent_app_type] => 1 [patent_app_number] => 7/896872 [patent_app_country] => US [patent_app_date] => 1992-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 5067 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258321.pdf [firstpage_image] =>[orig_patent_app_number] => 896872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2958239 [patent_doc_number] => 05198386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-30 [patent_title] => 'Method of making stacked capacitors for DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/895520 [patent_app_country] => US [patent_app_date] => 1992-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4231 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/198/05198386.pdf [firstpage_image] =>[orig_patent_app_number] => 895520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2966834 [patent_doc_number] => 05202280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/894938 [patent_app_country] => US [patent_app_date] => 1992-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 1937 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202280.pdf [firstpage_image] =>[orig_patent_app_number] => 894938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2909492 [patent_doc_number] => 05227326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method for fabricating non-volatile memory cells, arrays of non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 7/894171 [patent_app_country] => US [patent_app_date] => 1992-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 23 [patent_no_of_words] => 3605 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227326.pdf [firstpage_image] =>[orig_patent_app_number] => 894171 [rel_patent_id] =>[rel_patent_doc_number] =>)