Search

Tom Thomas

Supervisory Patent Examiner (ID: 139, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
2899, 1104, 2893, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2933594 [patent_doc_number] => 05246874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Method of making fast access AMG EPROM' [patent_app_type] => 1 [patent_app_number] => 7/892502 [patent_app_country] => US [patent_app_date] => 1992-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 3047 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/246/05246874.pdf [firstpage_image] =>[orig_patent_app_number] => 892502 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/892502
Method of making fast access AMG EPROM Jun 1, 1992 Issued
07/892259 SEGMENT-ERASABLE FLASH EPROM Jun 1, 1992 Abandoned
Array ( [id] => 3411025 [patent_doc_number] => 05411908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Flash EEPROM array with P-tank insulated from substrate by deep N-tank' [patent_app_type] => 1 [patent_app_number] => 7/890577 [patent_app_country] => US [patent_app_date] => 1992-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3523 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/411/05411908.pdf [firstpage_image] =>[orig_patent_app_number] => 890577 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/890577
Flash EEPROM array with P-tank insulated from substrate by deep N-tank May 27, 1992 Issued
Array ( [id] => 2890418 [patent_doc_number] => 05270238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method of making a semiconductor memory device having a double-stacked capacitor structure' [patent_app_type] => 1 [patent_app_number] => 7/887544 [patent_app_country] => US [patent_app_date] => 1992-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2990 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270238.pdf [firstpage_image] =>[orig_patent_app_number] => 887544 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/887544
Method of making a semiconductor memory device having a double-stacked capacitor structure May 21, 1992 Issued
07/885700 TEMPERATURE INDEPENDENT RESISTOR AND METHOD FOR FORMING THE SAME May 18, 1992 Abandoned
Array ( [id] => 3075682 [patent_doc_number] => 05322804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps' [patent_app_type] => 1 [patent_app_number] => 7/882070 [patent_app_country] => US [patent_app_date] => 1992-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7159 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/322/05322804.pdf [firstpage_image] =>[orig_patent_app_number] => 882070 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/882070
Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps May 11, 1992 Issued
Array ( [id] => 2918370 [patent_doc_number] => 05234857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Method of making semiconductor device having a capacitor of large capacitance' [patent_app_type] => 1 [patent_app_number] => 7/880736 [patent_app_country] => US [patent_app_date] => 1992-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 3783 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/234/05234857.pdf [firstpage_image] =>[orig_patent_app_number] => 880736 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/880736
Method of making semiconductor device having a capacitor of large capacitance May 7, 1992 Issued
Array ( [id] => 2931328 [patent_doc_number] => 05188973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-23 [patent_title] => 'Method of manufacturing SOI semiconductor element' [patent_app_type] => 1 [patent_app_number] => 7/877446 [patent_app_country] => US [patent_app_date] => 1992-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 5374 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/188/05188973.pdf [firstpage_image] =>[orig_patent_app_number] => 877446 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/877446
Method of manufacturing SOI semiconductor element Apr 29, 1992 Issued
Array ( [id] => 2889575 [patent_doc_number] => 05210049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Method of making a solid state image sensor' [patent_app_type] => 1 [patent_app_number] => 7/874880 [patent_app_country] => US [patent_app_date] => 1992-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2848 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210049.pdf [firstpage_image] =>[orig_patent_app_number] => 874880 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/874880
Method of making a solid state image sensor Apr 27, 1992 Issued
Array ( [id] => 3017256 [patent_doc_number] => 05302540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Method of making capacitor' [patent_app_type] => 1 [patent_app_number] => 7/872514 [patent_app_country] => US [patent_app_date] => 1992-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 1958 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/302/05302540.pdf [firstpage_image] =>[orig_patent_app_number] => 872514 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/872514
Method of making capacitor Apr 22, 1992 Issued
Array ( [id] => 3480716 [patent_doc_number] => 05405810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Alignment method and apparatus' [patent_app_type] => 1 [patent_app_number] => 7/869174 [patent_app_country] => US [patent_app_date] => 1992-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 9940 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405810.pdf [firstpage_image] =>[orig_patent_app_number] => 869174 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/869174
Alignment method and apparatus Apr 15, 1992 Issued
Array ( [id] => 3049172 [patent_doc_number] => 05324680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Semiconductor memory device and the fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 7/867856 [patent_app_country] => US [patent_app_date] => 1992-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2754 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324680.pdf [firstpage_image] =>[orig_patent_app_number] => 867856 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/867856
Semiconductor memory device and the fabrication method thereof Apr 12, 1992 Issued
Array ( [id] => 2952247 [patent_doc_number] => 05242845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Method of production of vertical MOS transistor' [patent_app_type] => 1 [patent_app_number] => 7/866418 [patent_app_country] => US [patent_app_date] => 1992-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 3665 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/242/05242845.pdf [firstpage_image] =>[orig_patent_app_number] => 866418 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/866418
Method of production of vertical MOS transistor Apr 9, 1992 Issued
Array ( [id] => 2978698 [patent_doc_number] => 05204280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Process for fabricating multiple pillars inside a dram trench for increased capacitor surface' [patent_app_type] => 1 [patent_app_number] => 7/865505 [patent_app_country] => US [patent_app_date] => 1992-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2991 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204280.pdf [firstpage_image] =>[orig_patent_app_number] => 865505 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/865505
Process for fabricating multiple pillars inside a dram trench for increased capacitor surface Apr 8, 1992 Issued
Array ( [id] => 2865947 [patent_doc_number] => 05162253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Method of producing capacitive element integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/863105 [patent_app_country] => US [patent_app_date] => 1992-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2739 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162253.pdf [firstpage_image] =>[orig_patent_app_number] => 863105 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/863105
Method of producing capacitive element integrated circuit Apr 2, 1992 Issued
Array ( [id] => 2909474 [patent_doc_number] => 05227325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Method of forming a capacitor' [patent_app_type] => 1 [patent_app_number] => 7/862526 [patent_app_country] => US [patent_app_date] => 1992-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3317 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227325.pdf [firstpage_image] =>[orig_patent_app_number] => 862526 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/862526
Method of forming a capacitor Apr 1, 1992 Issued
Array ( [id] => 2930245 [patent_doc_number] => 05219782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Sublithographic antifuse method for manufacturing' [patent_app_type] => 1 [patent_app_number] => 7/860473 [patent_app_country] => US [patent_app_date] => 1992-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3221 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/219/05219782.pdf [firstpage_image] =>[orig_patent_app_number] => 860473 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/860473
Sublithographic antifuse method for manufacturing Mar 29, 1992 Issued
Array ( [id] => 3091696 [patent_doc_number] => 05290727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors' [patent_app_type] => 1 [patent_app_number] => 7/860370 [patent_app_country] => US [patent_app_date] => 1992-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3348 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/290/05290727.pdf [firstpage_image] =>[orig_patent_app_number] => 860370 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/860370
Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors Mar 29, 1992 Issued
Array ( [id] => 2952171 [patent_doc_number] => 05242841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate' [patent_app_type] => 1 [patent_app_number] => 7/857360 [patent_app_country] => US [patent_app_date] => 1992-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 5006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/242/05242841.pdf [firstpage_image] =>[orig_patent_app_number] => 857360 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/857360
Method of making LDMOS transistor with self-aligned source/backgate and photo-aligned gate Mar 24, 1992 Issued
Array ( [id] => 2932837 [patent_doc_number] => 05229311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method of reducing hot-electron degradation in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/859264 [patent_app_country] => US [patent_app_date] => 1992-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229311.pdf [firstpage_image] =>[orig_patent_app_number] => 859264 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/859264
Method of reducing hot-electron degradation in semiconductor devices Mar 24, 1992 Issued
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