| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2784801
[patent_doc_number] => 05155058
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Method of making semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/855498
[patent_app_country] => US
[patent_app_date] => 1992-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 4421
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/155/05155058.pdf
[firstpage_image] =>[orig_patent_app_number] => 855498
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/855498 | Method of making semiconductor memory device | Mar 22, 1992 | Issued |
Array
(
[id] => 2930263
[patent_doc_number] => 05219783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Method of making semiconductor well structure'
[patent_app_type] => 1
[patent_app_number] => 7/856008
[patent_app_country] => US
[patent_app_date] => 1992-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3393
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/219/05219783.pdf
[firstpage_image] =>[orig_patent_app_number] => 856008
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/856008 | Method of making semiconductor well structure | Mar 19, 1992 | Issued |
Array
(
[id] => 2865853
[patent_doc_number] => 05162248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing'
[patent_app_type] => 1
[patent_app_number] => 7/850746
[patent_app_country] => US
[patent_app_date] => 1992-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2696
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/162/05162248.pdf
[firstpage_image] =>[orig_patent_app_number] => 850746
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/850746 | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Mar 12, 1992 | Issued |
Array
(
[id] => 2960610
[patent_doc_number] => 05273926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity'
[patent_app_type] => 1
[patent_app_number] => 7/850209
[patent_app_country] => US
[patent_app_date] => 1992-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 2694
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/273/05273926.pdf
[firstpage_image] =>[orig_patent_app_number] => 850209
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/850209 | Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity | Mar 11, 1992 | Issued |
Array
(
[id] => 2930208
[patent_doc_number] => 05219780
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Method for fabricating a semiconductor memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/849916
[patent_app_country] => US
[patent_app_date] => 1992-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 1464
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/219/05219780.pdf
[firstpage_image] =>[orig_patent_app_number] => 849916
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/849916 | Method for fabricating a semiconductor memory cell | Mar 11, 1992 | Issued |
Array
(
[id] => 2909456
[patent_doc_number] => 05227324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-13
[patent_title] => 'Gate array and manufacturing method of semiconductor memory device using the same'
[patent_app_type] => 1
[patent_app_number] => 7/849348
[patent_app_country] => US
[patent_app_date] => 1992-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 2815
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/227/05227324.pdf
[firstpage_image] =>[orig_patent_app_number] => 849348
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/849348 | Gate array and manufacturing method of semiconductor memory device using the same | Mar 10, 1992 | Issued |
Array
(
[id] => 2948408
[patent_doc_number] => 05262343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'DRAM stacked capacitor fabrication process'
[patent_app_type] => 1
[patent_app_number] => 7/852822
[patent_app_country] => US
[patent_app_date] => 1992-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 3582
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/262/05262343.pdf
[firstpage_image] =>[orig_patent_app_number] => 852822
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/852822 | DRAM stacked capacitor fabrication process | Mar 5, 1992 | Issued |
Array
(
[id] => 2974189
[patent_doc_number] => 05208180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-04
[patent_title] => 'Method of forming a capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/846215
[patent_app_country] => US
[patent_app_date] => 1992-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 13
[patent_no_of_words] => 2480
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 377
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/208/05208180.pdf
[firstpage_image] =>[orig_patent_app_number] => 846215
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/846215 | Method of forming a capacitor | Mar 3, 1992 | Issued |
Array
(
[id] => 3036994
[patent_doc_number] => 05372969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-13
[patent_title] => 'Low-RC multi-level interconnect technology for high-performance integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/845125
[patent_app_country] => US
[patent_app_date] => 1992-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 26
[patent_no_of_words] => 4443
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/372/05372969.pdf
[firstpage_image] =>[orig_patent_app_number] => 845125
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/845125 | Low-RC multi-level interconnect technology for high-performance integrated circuits | Mar 2, 1992 | Issued |
| 07/844088 | TRANSISTOR AND METHOD OF FORMATION AND LOGIC GATES FORMED THEREFROM | Mar 1, 1992 | Abandoned |
Array
(
[id] => 3043353
[patent_doc_number] => 05286666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Method of producing semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/843599
[patent_app_country] => US
[patent_app_date] => 1992-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4728
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 328
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/286/05286666.pdf
[firstpage_image] =>[orig_patent_app_number] => 843599
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/843599 | Method of producing semiconductor memory device | Feb 27, 1992 | Issued |
| 07/841370 | OZONE GAS PROCESSING FOR FERROELECTRIC MEMORY CIRCUITS | Feb 24, 1992 | Abandoned |
Array
(
[id] => 3091680
[patent_doc_number] => 05290726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-01
[patent_title] => 'DRAM cells having stacked capacitors of fin structures and method of making thereof'
[patent_app_type] => 1
[patent_app_number] => 7/836690
[patent_app_country] => US
[patent_app_date] => 1992-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 2326
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/290/05290726.pdf
[firstpage_image] =>[orig_patent_app_number] => 836690
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/836690 | DRAM cells having stacked capacitors of fin structures and method of making thereof | Feb 17, 1992 | Issued |
Array
(
[id] => 2899027
[patent_doc_number] => 05217918
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-08
[patent_title] => 'Method of manufacturing a highly integrated semiconductor memory device with trench capacitors and stacked capacitors'
[patent_app_type] => 1
[patent_app_number] => 7/832328
[patent_app_country] => US
[patent_app_date] => 1992-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 3039
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/217/05217918.pdf
[firstpage_image] =>[orig_patent_app_number] => 832328
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/832328 | Method of manufacturing a highly integrated semiconductor memory device with trench capacitors and stacked capacitors | Feb 6, 1992 | Issued |
Array
(
[id] => 3093517
[patent_doc_number] => 05298434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/832694
[patent_app_country] => US
[patent_app_date] => 1992-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1469
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/298/05298434.pdf
[firstpage_image] =>[orig_patent_app_number] => 832694
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/832694 | Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits | Feb 6, 1992 | Issued |
Array
(
[id] => 2802436
[patent_doc_number] => 05145801
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-08
[patent_title] => 'Method of increasing the surface area of a mini-stacked capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/832264
[patent_app_country] => US
[patent_app_date] => 1992-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3338
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 355
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/145/05145801.pdf
[firstpage_image] =>[orig_patent_app_number] => 832264
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/832264 | Method of increasing the surface area of a mini-stacked capacitor | Feb 6, 1992 | Issued |
Array
(
[id] => 2989126
[patent_doc_number] => 05346842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Method of making alternate metal/source virtual ground flash EPROM cell array'
[patent_app_type] => 1
[patent_app_number] => 7/830938
[patent_app_country] => US
[patent_app_date] => 1992-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 27
[patent_no_of_words] => 3475
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 391
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/346/05346842.pdf
[firstpage_image] =>[orig_patent_app_number] => 830938
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830938 | Method of making alternate metal/source virtual ground flash EPROM cell array | Feb 3, 1992 | Issued |
Array
(
[id] => 2893115
[patent_doc_number] => 05240866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Method for characterizing failed circuits on semiconductor wafers'
[patent_app_type] => 1
[patent_app_number] => 7/829634
[patent_app_country] => US
[patent_app_date] => 1992-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2915
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/240/05240866.pdf
[firstpage_image] =>[orig_patent_app_number] => 829634
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/829634 | Method for characterizing failed circuits on semiconductor wafers | Feb 2, 1992 | Issued |
Array
(
[id] => 3456691
[patent_doc_number] => 05401716
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-28
[patent_title] => 'Method for manufacturing superconducting patterns'
[patent_app_type] => 1
[patent_app_number] => 7/829531
[patent_app_country] => US
[patent_app_date] => 1992-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2408
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/401/05401716.pdf
[firstpage_image] =>[orig_patent_app_number] => 829531
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/829531 | Method for manufacturing superconducting patterns | Feb 2, 1992 | Issued |
Array
(
[id] => 2986043
[patent_doc_number] => 05212107
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-18
[patent_title] => 'Wiring method for semiconductor integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/830338
[patent_app_country] => US
[patent_app_date] => 1992-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3097
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/212/05212107.pdf
[firstpage_image] =>[orig_patent_app_number] => 830338
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830338 | Wiring method for semiconductor integrated circuits | Jan 30, 1992 | Issued |