Search

Tom Thomas

Supervisory Patent Examiner (ID: 139, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
2899, 1104, 2893, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2920946 [patent_doc_number] => 05192700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Method of making field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/828374 [patent_app_country] => US [patent_app_date] => 1992-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3843 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/192/05192700.pdf [firstpage_image] =>[orig_patent_app_number] => 828374 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/828374
Method of making field effect transistor Jan 29, 1992 Issued
Array ( [id] => 2894638 [patent_doc_number] => 05183772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Manufacturing method for a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/824885 [patent_app_country] => US [patent_app_date] => 1992-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/183/05183772.pdf [firstpage_image] =>[orig_patent_app_number] => 824885 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/824885
Manufacturing method for a DRAM cell Jan 21, 1992 Issued
07/823858 REDUCTION OF PARASITIC EFFECTS IN FLOATING BODY MOSFETS Jan 21, 1992 Abandoned
Array ( [id] => 3014844 [patent_doc_number] => 05340762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Method of making small contactless RAM cell' [patent_app_type] => 1 [patent_app_number] => 7/822390 [patent_app_country] => US [patent_app_date] => 1992-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 12128 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/340/05340762.pdf [firstpage_image] =>[orig_patent_app_number] => 822390 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/822390
Method of making small contactless RAM cell Jan 15, 1992 Issued
Array ( [id] => 2973837 [patent_doc_number] => 05225363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Trench capacitor DRAM cell and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 7/823804 [patent_app_country] => US [patent_app_date] => 1992-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3305 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225363.pdf [firstpage_image] =>[orig_patent_app_number] => 823804 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/823804
Trench capacitor DRAM cell and method of manufacture Jan 14, 1992 Issued
Array ( [id] => 2974902 [patent_doc_number] => 05256583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Mask surrogate semiconductor process with polysilicon gate protection' [patent_app_type] => 1 [patent_app_number] => 7/817867 [patent_app_country] => US [patent_app_date] => 1992-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 7313 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/256/05256583.pdf [firstpage_image] =>[orig_patent_app_number] => 817867 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/817867
Mask surrogate semiconductor process with polysilicon gate protection Jan 6, 1992 Issued
Array ( [id] => 2894658 [patent_doc_number] => 05183773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Method of manufacturing semiconductor device including such input protection transistor' [patent_app_type] => 1 [patent_app_number] => 7/817190 [patent_app_country] => US [patent_app_date] => 1992-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 52 [patent_no_of_words] => 6443 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/183/05183773.pdf [firstpage_image] =>[orig_patent_app_number] => 817190 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/817190
Method of manufacturing semiconductor device including such input protection transistor Jan 5, 1992 Issued
07/816456 ADVANCED LOW RC MULTI-LEVEL INTERCONNECT TECHNOLOGY FOR HIGH PERFORMANCE INTEGRATED CIRCUITS Dec 30, 1991 Abandoned
Array ( [id] => 2936739 [patent_doc_number] => 05190887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-02 [patent_title] => 'Method of making electrically erasable and electrically programmable memory cell with extended cycling endurance' [patent_app_type] => 1 [patent_app_number] => 7/815946 [patent_app_country] => US [patent_app_date] => 1991-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4821 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/190/05190887.pdf [firstpage_image] =>[orig_patent_app_number] => 815946 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/815946
Method of making electrically erasable and electrically programmable memory cell with extended cycling endurance Dec 29, 1991 Issued
Array ( [id] => 3045608 [patent_doc_number] => 05304505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells' [patent_app_type] => 1 [patent_app_number] => 7/813374 [patent_app_country] => US [patent_app_date] => 1991-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 9291 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304505.pdf [firstpage_image] =>[orig_patent_app_number] => 813374 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/813374
Process for EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells Dec 22, 1991 Issued
07/816428 METHOD FOR FABRICATING NON-VOLATILE MEMORY CELLS,ARRAYS OF NON-VOLITILE MEMORY CELLS Dec 22, 1991 Abandoned
Array ( [id] => 2950609 [patent_doc_number] => 05221635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-22 [patent_title] => 'Method of making a field-effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/808826 [patent_app_country] => US [patent_app_date] => 1991-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2059 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/221/05221635.pdf [firstpage_image] =>[orig_patent_app_number] => 808826 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/808826
Method of making a field-effect transistor Dec 16, 1991 Issued
Array ( [id] => 2894676 [patent_doc_number] => 05183774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Method of making a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/807659 [patent_app_country] => US [patent_app_date] => 1991-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2731 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/183/05183774.pdf [firstpage_image] =>[orig_patent_app_number] => 807659 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/807659
Method of making a semiconductor memory device Dec 15, 1991 Issued
Array ( [id] => 2910026 [patent_doc_number] => 05236859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Method of making stacked-capacitor for a dram cell same' [patent_app_type] => 1 [patent_app_number] => 7/804384 [patent_app_country] => US [patent_app_date] => 1991-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2141 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/236/05236859.pdf [firstpage_image] =>[orig_patent_app_number] => 804384 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/804384
Method of making stacked-capacitor for a dram cell same Dec 9, 1991 Issued
Array ( [id] => 2933032 [patent_doc_number] => 05229322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method of making low resistance substrate or buried layer contact' [patent_app_type] => 1 [patent_app_number] => 7/804228 [patent_app_country] => US [patent_app_date] => 1991-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3830 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229322.pdf [firstpage_image] =>[orig_patent_app_number] => 804228 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/804228
Method of making low resistance substrate or buried layer contact Dec 4, 1991 Issued
Array ( [id] => 2823135 [patent_doc_number] => 05169803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of filling contact holes of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/798960 [patent_app_country] => US [patent_app_date] => 1991-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 9646 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169803.pdf [firstpage_image] =>[orig_patent_app_number] => 798960 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/798960
Method of filling contact holes of a semiconductor device Nov 26, 1991 Issued
07/797348 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF PRODUCING THE SAME USING MASTER SLICE APPROACH Nov 24, 1991 Abandoned
Array ( [id] => 2852170 [patent_doc_number] => 05134085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 7/796099 [patent_app_country] => US [patent_app_date] => 1991-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4962 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134085.pdf [firstpage_image] =>[orig_patent_app_number] => 796099 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/796099
Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories Nov 20, 1991 Issued
Array ( [id] => 2857471 [patent_doc_number] => 05149668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/795338 [patent_app_country] => US [patent_app_date] => 1991-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 2533 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/149/05149668.pdf [firstpage_image] =>[orig_patent_app_number] => 795338 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/795338
Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits Nov 18, 1991 Issued
Array ( [id] => 2866333 [patent_doc_number] => 05153144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-06 [patent_title] => 'Method of making tunnel EEPROM' [patent_app_type] => 1 [patent_app_number] => 7/794648 [patent_app_country] => US [patent_app_date] => 1991-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 8262 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/153/05153144.pdf [firstpage_image] =>[orig_patent_app_number] => 794648 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/794648
Method of making tunnel EEPROM Nov 17, 1991 Issued
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