Tom Thomas

Array ( [id] => 2823023 [patent_doc_number] => 05169797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Manufacturing method for semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 7/750586 [patent_app_country] => US [patent_app_date] => 1991-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 2083 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169797.pdf [firstpage_image] =>[orig_patent_app_number] => 750586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2976332 [patent_doc_number] => 05252508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-12 [patent_title] => 'Apparatus and method for the fabrication of semiconductor circuits' [patent_app_type] => 1 [patent_app_number] => 7/747672 [patent_app_country] => US [patent_app_date] => 1991-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/252/05252508.pdf [firstpage_image] =>[orig_patent_app_number] => 747672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2776136 [patent_doc_number] => 05151380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'Method of making top buss virtual phase frame interline transfer CCD image sensor' [patent_app_type] => 1 [patent_app_number] => 7/747036 [patent_app_country] => US [patent_app_date] => 1991-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7587 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151380.pdf [firstpage_image] =>[orig_patent_app_number] => 747036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2822424 [patent_doc_number] => 05173437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-22 [patent_title] => 'Double polysilicon capacitor formation compatable with submicron processing' [patent_app_type] => 1 [patent_app_number] => 7/739222 [patent_app_country] => US [patent_app_date] => 1991-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2781 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/173/05173437.pdf [firstpage_image] =>[orig_patent_app_number] => 739222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2804473 [patent_doc_number] => 05147816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-15 [patent_title] => 'Method of making nonvolatile memory array having cells with two tunelling windows' [patent_app_type] => 1 [patent_app_number] => 7/736338 [patent_app_country] => US [patent_app_date] => 1991-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7217 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/147/05147816.pdf [firstpage_image] =>[orig_patent_app_number] => 736338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772428 [patent_doc_number] => 05132240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/734470 [patent_app_country] => US [patent_app_date] => 1991-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3377 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132240.pdf [firstpage_image] =>[orig_patent_app_number] => 734470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2802418 [patent_doc_number] => 05145800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'Method of wiring for power supply to large-scale integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/731616 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4730 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/145/05145800.pdf [firstpage_image] =>[orig_patent_app_number] => 731616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2780176 [patent_doc_number] => 05164218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Semiconductor device and a method for producing the same' [patent_app_type] => 1 [patent_app_number] => 7/731268 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 5398 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/164/05164218.pdf [firstpage_image] =>[orig_patent_app_number] => 731268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2853336 [patent_doc_number] => 05112766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'Method of manufacturing field effect transistors' [patent_app_type] => 1 [patent_app_number] => 7/730626 [patent_app_country] => US [patent_app_date] => 1991-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 3975 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/112/05112766.pdf [firstpage_image] =>[orig_patent_app_number] => 730626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2857413 [patent_doc_number] => 05149665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'Conductive source line for high density programmable read-only memory applications' [patent_app_type] => 1 [patent_app_number] => 7/727702 [patent_app_country] => US [patent_app_date] => 1991-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 3753 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/149/05149665.pdf [firstpage_image] =>[orig_patent_app_number] => 727702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3006810 [patent_doc_number] => 05354716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Method for forming a DRAM memory cell with tapered capacitor electrodes' [patent_app_type] => 1 [patent_app_number] => 7/727678 [patent_app_country] => US [patent_app_date] => 1991-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4422 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/354/05354716.pdf [firstpage_image] =>[orig_patent_app_number] => 727678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2931383 [patent_doc_number] => 05188976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-23 [patent_title] => 'Manufacturing method of non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/727052 [patent_app_country] => US [patent_app_date] => 1991-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 9592 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/188/05188976.pdf [firstpage_image] =>[orig_patent_app_number] => 727052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2865872 [patent_doc_number] => 05162249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Method of making semiconductor memory device having a double stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 7/726863 [patent_app_country] => US [patent_app_date] => 1991-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 4875 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162249.pdf [firstpage_image] =>[orig_patent_app_number] => 726863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2891377 [patent_doc_number] => 05177030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Method of making self-aligned vertical intrinsic resistance' [patent_app_type] => 1 [patent_app_number] => 7/725138 [patent_app_country] => US [patent_app_date] => 1991-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177030.pdf [firstpage_image] =>[orig_patent_app_number] => 725138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2857158 [patent_doc_number] => 05084406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-28 [patent_title] => 'Method for forming low resistance DRAM digit-line' [patent_app_type] => 1 [patent_app_number] => 7/724026 [patent_app_country] => US [patent_app_date] => 1991-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2717 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/084/05084406.pdf [firstpage_image] =>[orig_patent_app_number] => 724026 [rel_patent_id] =>[rel_patent_doc_number] =>)