
Tom Thomas
Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2893, 2899, 2811 |
| Total Applications | 746 |
| Issued Applications | 628 |
| Pending Applications | 6 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2713091
[patent_doc_number] => 05053350
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-01
[patent_title] => 'Method of making trench MOSFET capacitor cell for analog signal processing'
[patent_app_type] => 1
[patent_app_number] => 7/683509
[patent_app_country] => US
[patent_app_date] => 1991-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 17
[patent_no_of_words] => 4071
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 365
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/053/05053350.pdf
[firstpage_image] =>[orig_patent_app_number] => 683509
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/683509 | Method of making trench MOSFET capacitor cell for analog signal processing | Apr 7, 1991 | Issued |
Array
(
[id] => 2788444
[patent_doc_number] => 05135882
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-04
[patent_title] => 'Technique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnect'
[patent_app_type] => 1
[patent_app_number] => 7/680224
[patent_app_country] => US
[patent_app_date] => 1991-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 3054
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 413
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/135/05135882.pdf
[firstpage_image] =>[orig_patent_app_number] => 680224
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/680224 | Technique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnect | Apr 3, 1991 | Issued |
Array
(
[id] => 2784765
[patent_doc_number] => 05155056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Process for formation of cells having self-aligned capacitor contacts, and structure thereof'
[patent_app_type] => 1
[patent_app_number] => 7/679956
[patent_app_country] => US
[patent_app_date] => 1991-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 1023
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/155/05155056.pdf
[firstpage_image] =>[orig_patent_app_number] => 679956
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/679956 | Process for formation of cells having self-aligned capacitor contacts, and structure thereof | Apr 2, 1991 | Issued |
Array
(
[id] => 2966655
[patent_doc_number] => 05202272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Field effect transistor formed with deep-submicron gate'
[patent_app_type] => 1
[patent_app_number] => 7/744724
[patent_app_country] => US
[patent_app_date] => 1991-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 3523
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/202/05202272.pdf
[firstpage_image] =>[orig_patent_app_number] => 744724
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/744724 | Field effect transistor formed with deep-submicron gate | Mar 24, 1991 | Issued |
Array
(
[id] => 2713117
[patent_doc_number] => 05053351
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-01
[patent_title] => 'Method of making stacked E-cell capacitor DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 7/671312
[patent_app_country] => US
[patent_app_date] => 1991-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2786
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/053/05053351.pdf
[firstpage_image] =>[orig_patent_app_number] => 671312
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/671312 | Method of making stacked E-cell capacitor DRAM cell | Mar 18, 1991 | Issued |
Array
(
[id] => 2783308
[patent_doc_number] => 05141880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Manufacturing method of a junction gate field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/669080
[patent_app_country] => US
[patent_app_date] => 1991-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 34
[patent_no_of_words] => 4449
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/141/05141880.pdf
[firstpage_image] =>[orig_patent_app_number] => 669080
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/669080 | Manufacturing method of a junction gate field effect transistor | Mar 11, 1991 | Issued |
Array
(
[id] => 2692785
[patent_doc_number] => 05064777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-12
[patent_title] => 'Fabrication method for a double trench memory cell device'
[patent_app_type] => 1
[patent_app_number] => 7/664684
[patent_app_country] => US
[patent_app_date] => 1991-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3297
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/064/05064777.pdf
[firstpage_image] =>[orig_patent_app_number] => 664684
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/664684 | Fabrication method for a double trench memory cell device | Mar 3, 1991 | Issued |
Array
(
[id] => 2877620
[patent_doc_number] => 05185283
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-09
[patent_title] => 'Method of making master slice type integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/666452
[patent_app_country] => US
[patent_app_date] => 1991-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 30
[patent_no_of_words] => 13018
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/185/05185283.pdf
[firstpage_image] =>[orig_patent_app_number] => 666452
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/666452 | Method of making master slice type integrated circuit device | Mar 3, 1991 | Issued |
Array
(
[id] => 2881924
[patent_doc_number] => 05108938
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Method of making a trench gate complimentary metal oxide semiconductor transistor'
[patent_app_type] => 1
[patent_app_number] => 7/664464
[patent_app_country] => US
[patent_app_date] => 1991-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 11
[patent_no_of_words] => 3609
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 220
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/108/05108938.pdf
[firstpage_image] =>[orig_patent_app_number] => 664464
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/664464 | Method of making a trench gate complimentary metal oxide semiconductor transistor | Feb 28, 1991 | Issued |
Array
(
[id] => 2800703
[patent_doc_number] => 05124273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Automatic wiring method for semiconductor integrated circuit devices'
[patent_app_type] => 1
[patent_app_number] => 7/691613
[patent_app_country] => US
[patent_app_date] => 1991-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5479
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/124/05124273.pdf
[firstpage_image] =>[orig_patent_app_number] => 691613
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/691613 | Automatic wiring method for semiconductor integrated circuit devices | Feb 26, 1991 | Issued |
Array
(
[id] => 2771667
[patent_doc_number] => 05075248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-24
[patent_title] => 'Method of making DRAM having a side wall doped trench and stacked capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 7/660151
[patent_app_country] => US
[patent_app_date] => 1991-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 5681
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 675
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/075/05075248.pdf
[firstpage_image] =>[orig_patent_app_number] => 660151
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/660151 | Method of making DRAM having a side wall doped trench and stacked capacitor structure | Feb 19, 1991 | Issued |
Array
(
[id] => 2835752
[patent_doc_number] => 05160491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-03
[patent_title] => 'Method of making a vertical MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 7/656522
[patent_app_country] => US
[patent_app_date] => 1991-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 6432
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/160/05160491.pdf
[firstpage_image] =>[orig_patent_app_number] => 656522
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/656522 | Method of making a vertical MOS transistor | Feb 18, 1991 | Issued |
Array
(
[id] => 2783438
[patent_doc_number] => 05141886
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Vertical floating-gate transistor'
[patent_app_type] => 1
[patent_app_number] => 7/656392
[patent_app_country] => US
[patent_app_date] => 1991-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3394
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/141/05141886.pdf
[firstpage_image] =>[orig_patent_app_number] => 656392
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/656392 | Vertical floating-gate transistor | Feb 18, 1991 | Issued |
Array
(
[id] => 2816449
[patent_doc_number] => 05081054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-14
[patent_title] => 'Fabrication process for programmable and erasable MOS memory device'
[patent_app_type] => 1
[patent_app_number] => 7/652293
[patent_app_country] => US
[patent_app_date] => 1991-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 27
[patent_no_of_words] => 3481
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 357
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/081/05081054.pdf
[firstpage_image] =>[orig_patent_app_number] => 652293
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/652293 | Fabrication process for programmable and erasable MOS memory device | Feb 4, 1991 | Issued |
Array
(
[id] => 2845033
[patent_doc_number] => 05106774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Method of making trench type dynamic random access memory device'
[patent_app_type] => 1
[patent_app_number] => 7/650992
[patent_app_country] => US
[patent_app_date] => 1991-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 38
[patent_no_of_words] => 7487
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/106/05106774.pdf
[firstpage_image] =>[orig_patent_app_number] => 650992
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/650992 | Method of making trench type dynamic random access memory device | Feb 3, 1991 | Issued |
Array
(
[id] => 2789523
[patent_doc_number] => 05102819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-07
[patent_title] => 'Method of making a DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 7/644448
[patent_app_country] => US
[patent_app_date] => 1991-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 34
[patent_no_of_words] => 7461
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/102/05102819.pdf
[firstpage_image] =>[orig_patent_app_number] => 644448
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/644448 | Method of making a DRAM cell | Jan 22, 1991 | Issued |
Array
(
[id] => 2860430
[patent_doc_number] => 05082797
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-21
[patent_title] => 'Method of making stacked textured container capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/645086
[patent_app_country] => US
[patent_app_date] => 1991-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 2505
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 542
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/082/05082797.pdf
[firstpage_image] =>[orig_patent_app_number] => 645086
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/645086 | Method of making stacked textured container capacitor | Jan 21, 1991 | Issued |
Array
(
[id] => 2783475
[patent_doc_number] => 05141888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-25
[patent_title] => 'Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions'
[patent_app_type] => 1
[patent_app_number] => 7/642922
[patent_app_country] => US
[patent_app_date] => 1991-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 33
[patent_no_of_words] => 5839
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/141/05141888.pdf
[firstpage_image] =>[orig_patent_app_number] => 642922
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/642922 | Process of manufacturing semiconductor integrated circuit device having trench and field isolation regions | Jan 17, 1991 | Issued |
Array
(
[id] => 2973953
[patent_doc_number] => 05182224
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-26
[patent_title] => 'Method of making dynamic random access memory cell having a SDHT structure'
[patent_app_type] => 1
[patent_app_number] => 7/641621
[patent_app_country] => US
[patent_app_date] => 1991-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 4902
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/182/05182224.pdf
[firstpage_image] =>[orig_patent_app_number] => 641621
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/641621 | Method of making dynamic random access memory cell having a SDHT structure | Jan 15, 1991 | Issued |
| 07/637434 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME | Jan 3, 1991 | Abandoned |