Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
07/637434 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME Jan 3, 1991 Abandoned
Array ( [id] => 2931750 [patent_doc_number] => 05196363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Method of forming mist type dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 7/635728 [patent_app_country] => US [patent_app_date] => 1990-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2557 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196363.pdf [firstpage_image] =>[orig_patent_app_number] => 635728 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/635728
Method of forming mist type dynamic random access memory cell Dec 27, 1990 Issued
Array ( [id] => 2854808 [patent_doc_number] => 05166090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Method for manufacturing a semiconductor random access memory cell' [patent_app_type] => 1 [patent_app_number] => 7/639778 [patent_app_country] => US [patent_app_date] => 1990-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1790 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166090.pdf [firstpage_image] =>[orig_patent_app_number] => 639778 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/639778
Method for manufacturing a semiconductor random access memory cell Dec 13, 1990 Issued
Array ( [id] => 2973935 [patent_doc_number] => 05182223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-26 [patent_title] => 'Method of making an integrated circuit with capacitor' [patent_app_type] => 1 [patent_app_number] => 7/629922 [patent_app_country] => US [patent_app_date] => 1990-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 2401 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/182/05182223.pdf [firstpage_image] =>[orig_patent_app_number] => 629922 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/629922
Method of making an integrated circuit with capacitor Dec 11, 1990 Issued
Array ( [id] => 2679810 [patent_doc_number] => 05066606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Implant method for advanced stacked capacitors' [patent_app_type] => 1 [patent_app_number] => 7/624166 [patent_app_country] => US [patent_app_date] => 1990-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/066/05066606.pdf [firstpage_image] =>[orig_patent_app_number] => 624166 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/624166
Implant method for advanced stacked capacitors Dec 6, 1990 Issued
Array ( [id] => 2853250 [patent_doc_number] => 05112762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'High angle implant around top of trench to reduce gated diode leakage' [patent_app_type] => 1 [patent_app_number] => 7/622468 [patent_app_country] => US [patent_app_date] => 1990-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/112/05112762.pdf [firstpage_image] =>[orig_patent_app_number] => 622468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/622468
High angle implant around top of trench to reduce gated diode leakage Dec 4, 1990 Issued
Array ( [id] => 2920897 [patent_doc_number] => 05200354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Method for manufacturing dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 7/621872 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 7865 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 494 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200354.pdf [firstpage_image] =>[orig_patent_app_number] => 621872 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/621872
Method for manufacturing dynamic random access memory cell Dec 3, 1990 Issued
Array ( [id] => 2754359 [patent_doc_number] => 05043298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Process for manufacturing a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/619666 [patent_app_country] => US [patent_app_date] => 1990-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 83 [patent_no_of_words] => 7553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043298.pdf [firstpage_image] =>[orig_patent_app_number] => 619666 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/619666
Process for manufacturing a DRAM cell Nov 27, 1990 Issued
Array ( [id] => 2865890 [patent_doc_number] => 05162250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Method for interconnecting a filament channel transistor with a wordline conductor' [patent_app_type] => 1 [patent_app_number] => 7/618133 [patent_app_country] => US [patent_app_date] => 1990-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4095 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162250.pdf [firstpage_image] =>[orig_patent_app_number] => 618133 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/618133
Method for interconnecting a filament channel transistor with a wordline conductor Nov 25, 1990 Issued
Array ( [id] => 2787390 [patent_doc_number] => 05100825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'Method of making stacked surrounding reintrant wall capacitor' [patent_app_type] => 1 [patent_app_number] => 7/614892 [patent_app_country] => US [patent_app_date] => 1990-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2382 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/100/05100825.pdf [firstpage_image] =>[orig_patent_app_number] => 614892 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/614892
Method of making stacked surrounding reintrant wall capacitor Nov 15, 1990 Issued
Array ( [id] => 2686854 [patent_doc_number] => 05049517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Method for formation of a stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 7/612402 [patent_app_country] => US [patent_app_date] => 1990-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2996 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/049/05049517.pdf [firstpage_image] =>[orig_patent_app_number] => 612402 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/612402
Method for formation of a stacked capacitor Nov 6, 1990 Issued
Array ( [id] => 2709332 [patent_doc_number] => 05061653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-29 [patent_title] => 'Trench isolation process' [patent_app_type] => 1 [patent_app_number] => 7/605818 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 1605 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/061/05061653.pdf [firstpage_image] =>[orig_patent_app_number] => 605818 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/605818
Trench isolation process Oct 29, 1990 Issued
Array ( [id] => 2812228 [patent_doc_number] => 05086008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology' [patent_app_type] => 1 [patent_app_number] => 7/604995 [patent_app_country] => US [patent_app_date] => 1990-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1057 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086008.pdf [firstpage_image] =>[orig_patent_app_number] => 604995 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/604995
Process for obtaining high-voltage N channel transistors particularly for EEPROM memories with CMOS technology Oct 28, 1990 Issued
Array ( [id] => 2931771 [patent_doc_number] => 05196364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Method of making a stacked capacitor dram cell' [patent_app_type] => 1 [patent_app_number] => 7/602828 [patent_app_country] => US [patent_app_date] => 1990-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 554 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/196/05196364.pdf [firstpage_image] =>[orig_patent_app_number] => 602828 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/602828
Method of making a stacked capacitor dram cell Oct 23, 1990 Issued
Array ( [id] => 2668782 [patent_doc_number] => 05034336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Method of producing insulated gate bipolar tranistor' [patent_app_type] => 1 [patent_app_number] => 7/596562 [patent_app_country] => US [patent_app_date] => 1990-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2695 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 516 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034336.pdf [firstpage_image] =>[orig_patent_app_number] => 596562 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/596562
Method of producing insulated gate bipolar tranistor Oct 9, 1990 Issued
Array ( [id] => 2803766 [patent_doc_number] => 05114873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Method for manufacturing a stacked capacitor DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/592807 [patent_app_country] => US [patent_app_date] => 1990-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 2837 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/114/05114873.pdf [firstpage_image] =>[orig_patent_app_number] => 592807 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/592807
Method for manufacturing a stacked capacitor DRAM cell Oct 3, 1990 Issued
Array ( [id] => 2681476 [patent_doc_number] => 05045491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Method of making a nonvolatile memory array having cells with separate program and erase regions' [patent_app_type] => 1 [patent_app_number] => 7/589342 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5678 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/045/05045491.pdf [firstpage_image] =>[orig_patent_app_number] => 589342 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/589342
Method of making a nonvolatile memory array having cells with separate program and erase regions Sep 27, 1990 Issued
Array ( [id] => 2788462 [patent_doc_number] => 05135883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'Process for producing a stacked capacitor of a dram cell' [patent_app_type] => 1 [patent_app_number] => 7/582380 [patent_app_country] => US [patent_app_date] => 1990-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2362 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/135/05135883.pdf [firstpage_image] =>[orig_patent_app_number] => 582380 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/582380
Process for producing a stacked capacitor of a dram cell Sep 13, 1990 Issued
Array ( [id] => 2960151 [patent_doc_number] => RE034400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-05 [patent_title] => 'Method for fabricating isolation region in semiconductor devices' [patent_app_type] => 2 [patent_app_number] => 7/582000 [patent_app_country] => US [patent_app_date] => 1990-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2793 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/034/RE034400.pdf [firstpage_image] =>[orig_patent_app_number] => 582000 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/582000
Method for fabricating isolation region in semiconductor devices Sep 13, 1990 Issued
Array ( [id] => 2978718 [patent_doc_number] => 05204281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method of making dynamic random access memory cell having a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 7/576872 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204281.pdf [firstpage_image] =>[orig_patent_app_number] => 576872 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576872
Method of making dynamic random access memory cell having a trench capacitor Sep 3, 1990 Issued
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