Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2978718 [patent_doc_number] => 05204281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method of making dynamic random access memory cell having a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 7/576872 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204281.pdf [firstpage_image] =>[orig_patent_app_number] => 576872 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576872
Method of making dynamic random access memory cell having a trench capacitor Sep 3, 1990 Issued
Array ( [id] => 2671610 [patent_doc_number] => 05073515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode' [patent_app_type] => 1 [patent_app_number] => 7/572262 [patent_app_country] => US [patent_app_date] => 1990-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3171 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073515.pdf [firstpage_image] =>[orig_patent_app_number] => 572262 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/572262
Method for manufacturing a trench capacitor of a one-transistor memory cell in a semiconductor substrate with a self-aligned capacitor plate electrode Aug 26, 1990 Issued
Array ( [id] => 2804977 [patent_doc_number] => 05156993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-20 [patent_title] => 'Fabricating a memory cell with an improved capacitor' [patent_app_type] => 1 [patent_app_number] => 7/568945 [patent_app_country] => US [patent_app_date] => 1990-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 2159 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/156/05156993.pdf [firstpage_image] =>[orig_patent_app_number] => 568945 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/568945
Fabricating a memory cell with an improved capacitor Aug 16, 1990 Issued
Array ( [id] => 2679828 [patent_doc_number] => 05066607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Method of making a trench DRAM cell with dynamic gain' [patent_app_type] => 1 [patent_app_number] => 7/567989 [patent_app_country] => US [patent_app_date] => 1990-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4790 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/066/05066607.pdf [firstpage_image] =>[orig_patent_app_number] => 567989 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/567989
Method of making a trench DRAM cell with dynamic gain Aug 15, 1990 Issued
Array ( [id] => 2747584 [patent_doc_number] => 05021357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Method of making a dram cell with stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 7/561424 [patent_app_country] => US [patent_app_date] => 1990-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 119 [patent_no_of_words] => 14169 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021357.pdf [firstpage_image] =>[orig_patent_app_number] => 561424 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/561424
Method of making a dram cell with stacked capacitor Jul 31, 1990 Issued
Array ( [id] => 2848442 [patent_doc_number] => 05104821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'Method for fabricating stacked capacitors in a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/560755 [patent_app_country] => US [patent_app_date] => 1990-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/104/05104821.pdf [firstpage_image] =>[orig_patent_app_number] => 560755 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/560755
Method for fabricating stacked capacitors in a DRAM cell Jul 30, 1990 Issued
Array ( [id] => 2845051 [patent_doc_number] => 05106775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-21 [patent_title] => 'Process for manufacturing vertical dynamic random access memories' [patent_app_type] => 1 [patent_app_number] => 7/564470 [patent_app_country] => US [patent_app_date] => 1990-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5182 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/106/05106775.pdf [firstpage_image] =>[orig_patent_app_number] => 564470 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/564470
Process for manufacturing vertical dynamic random access memories Jul 29, 1990 Issued
Array ( [id] => 2850657 [patent_doc_number] => 05126279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique' [patent_app_type] => 1 [patent_app_number] => 7/559540 [patent_app_country] => US [patent_app_date] => 1990-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2357 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/126/05126279.pdf [firstpage_image] =>[orig_patent_app_number] => 559540 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/559540
Single polysilicon cross-coupled resistor, six-transistor SRAM cell design technique Jul 22, 1990 Issued
Array ( [id] => 2915312 [patent_doc_number] => 05179031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide' [patent_app_type] => 1 [patent_app_number] => 7/555345 [patent_app_country] => US [patent_app_date] => 1990-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 2895 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179031.pdf [firstpage_image] =>[orig_patent_app_number] => 555345 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/555345
Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide Jul 18, 1990 Issued
Array ( [id] => 2705945 [patent_doc_number] => 05013680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-07 [patent_title] => 'Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography' [patent_app_type] => 1 [patent_app_number] => 7/555980 [patent_app_country] => US [patent_app_date] => 1990-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 7459 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 690 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/013/05013680.pdf [firstpage_image] =>[orig_patent_app_number] => 555980 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/555980
Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography Jul 17, 1990 Issued
07/550610 HIGH DENSITY DYNAMIC RAM CELL Jul 9, 1990 Abandoned
Array ( [id] => 2723057 [patent_doc_number] => 05057447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Silicide/metal floating gate process' [patent_app_type] => 1 [patent_app_number] => 7/549862 [patent_app_country] => US [patent_app_date] => 1990-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4014 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057447.pdf [firstpage_image] =>[orig_patent_app_number] => 549862 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549862
Silicide/metal floating gate process Jul 8, 1990 Issued
Array ( [id] => 2781503 [patent_doc_number] => 05087588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-11 [patent_title] => 'Method of making a side wall contact with reactive ion etching' [patent_app_type] => 1 [patent_app_number] => 7/548335 [patent_app_country] => US [patent_app_date] => 1990-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3220 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/087/05087588.pdf [firstpage_image] =>[orig_patent_app_number] => 548335 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/548335
Method of making a side wall contact with reactive ion etching Jul 4, 1990 Issued
Array ( [id] => 2697987 [patent_doc_number] => 04988637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-01-29 [patent_title] => 'Method for fabricating a mesa transistor-trench capacitor memory cell structure' [patent_app_type] => 1 [patent_app_number] => 7/546194 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3265 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/988/04988637.pdf [firstpage_image] =>[orig_patent_app_number] => 546194 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546194
Method for fabricating a mesa transistor-trench capacitor memory cell structure Jun 28, 1990 Issued
Array ( [id] => 2686819 [patent_doc_number] => 05049515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Method of making a three-dimensional memory cell with integral select transistor' [patent_app_type] => 1 [patent_app_number] => 7/543043 [patent_app_country] => US [patent_app_date] => 1990-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4141 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/049/05049515.pdf [firstpage_image] =>[orig_patent_app_number] => 543043 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/543043
Method of making a three-dimensional memory cell with integral select transistor Jun 21, 1990 Issued
Array ( [id] => 2828500 [patent_doc_number] => 05128273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Method of making a dynamic random access memory cell with stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 7/536757 [patent_app_country] => US [patent_app_date] => 1990-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 89 [patent_no_of_words] => 6777 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128273.pdf [firstpage_image] =>[orig_patent_app_number] => 536757 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/536757
Method of making a dynamic random access memory cell with stacked capacitor Jun 11, 1990 Issued
Array ( [id] => 2669916 [patent_doc_number] => 05026659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-25 [patent_title] => 'Process for fabricating stacked trench capacitors of dynamic ram' [patent_app_type] => 1 [patent_app_number] => 7/534927 [patent_app_country] => US [patent_app_date] => 1990-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1389 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/026/05026659.pdf [firstpage_image] =>[orig_patent_app_number] => 534927 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/534927
Process for fabricating stacked trench capacitors of dynamic ram Jun 6, 1990 Issued
Array ( [id] => 2776063 [patent_doc_number] => 05151376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'Method of making polycrystalline silicon resistors for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/531012 [patent_app_country] => US [patent_app_date] => 1990-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2285 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151376.pdf [firstpage_image] =>[orig_patent_app_number] => 531012 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/531012
Method of making polycrystalline silicon resistors for integrated circuits May 30, 1990 Issued
Array ( [id] => 2851299 [patent_doc_number] => 05089436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Method for fabricating a semiconductor device by slope etching a polysiliow layer' [patent_app_type] => 1 [patent_app_number] => 7/519261 [patent_app_country] => US [patent_app_date] => 1990-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 2303 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089436.pdf [firstpage_image] =>[orig_patent_app_number] => 519261 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/519261
Method for fabricating a semiconductor device by slope etching a polysiliow layer May 1, 1990 Issued
Array ( [id] => 2765458 [patent_doc_number] => 05006481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Method of making a stacked capacitor DRAM cell' [patent_app_type] => 1 [patent_app_number] => 7/516271 [patent_app_country] => US [patent_app_date] => 1990-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2880 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/006/05006481.pdf [firstpage_image] =>[orig_patent_app_number] => 516271 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/516271
Method of making a stacked capacitor DRAM cell Apr 29, 1990 Issued
Menu