
Tom Thomas
Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2893, 2899, 2811 |
| Total Applications | 746 |
| Issued Applications | 628 |
| Pending Applications | 6 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2851259
[patent_doc_number] => 05089434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-18
[patent_title] => 'Mask surrogate semiconductor process employing dopant-opaque region'
[patent_app_type] => 1
[patent_app_number] => 7/467947
[patent_app_country] => US
[patent_app_date] => 1990-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 41
[patent_no_of_words] => 7312
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/089/05089434.pdf
[firstpage_image] =>[orig_patent_app_number] => 467947
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/467947 | Mask surrogate semiconductor process employing dopant-opaque region | Jan 21, 1990 | Issued |
| 07/467552 | TRENCH JFET INTEGRATED CIRCUIT ELEMENTS | Jan 18, 1990 | Abandoned |
Array
(
[id] => 2857380
[patent_doc_number] => 05084418
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-28
[patent_title] => 'Method of making an array device with buried interconnects'
[patent_app_type] => 1
[patent_app_number] => 7/465563
[patent_app_country] => US
[patent_app_date] => 1990-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 1462
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 97
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/084/05084418.pdf
[firstpage_image] =>[orig_patent_app_number] => 465563
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/465563 | Method of making an array device with buried interconnects | Jan 15, 1990 | Issued |
Array
(
[id] => 2668872
[patent_doc_number] => 05034341
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-23
[patent_title] => 'Method of making a memory cell array structure'
[patent_app_type] => 1
[patent_app_number] => 7/461998
[patent_app_country] => US
[patent_app_date] => 1990-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 8364
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/034/05034341.pdf
[firstpage_image] =>[orig_patent_app_number] => 461998
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/461998 | Method of making a memory cell array structure | Jan 7, 1990 | Issued |
| 07/461589 | SEMICONDUCTOR DEVICE HAVING TRENCH CAPACITOR AND MANUFACTURING METHOD THEREFOR | Jan 4, 1990 | Abandoned |
Array
(
[id] => 2693650
[patent_doc_number] => 05019522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-28
[patent_title] => 'Method of making topographic pattern delineated power MOSFET with profile tailored recessed source'
[patent_app_type] => 1
[patent_app_number] => 7/460258
[patent_app_country] => US
[patent_app_date] => 1990-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 40
[patent_no_of_words] => 7314
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[firstpage_image] =>[orig_patent_app_number] => 460258
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/460258 | Method of making topographic pattern delineated power MOSFET with profile tailored recessed source | Jan 1, 1990 | Issued |
Array
(
[id] => 2602483
[patent_doc_number] => 04948747
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-14
[patent_title] => 'Method of making an integrated circuit resistor'
[patent_app_type] => 1
[patent_app_number] => 7/451900
[patent_app_country] => US
[patent_app_date] => 1989-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2071
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[pdf_file] => patents/04/948/04948747.pdf
[firstpage_image] =>[orig_patent_app_number] => 451900
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/451900 | Method of making an integrated circuit resistor | Dec 17, 1989 | Issued |
Array
(
[id] => 2686837
[patent_doc_number] => 05049516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'Method of manufacturing semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/451066
[patent_app_country] => US
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[pdf_file] => patents/05/049/05049516.pdf
[firstpage_image] =>[orig_patent_app_number] => 451066
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/451066 | Method of manufacturing semiconductor memory device | Dec 14, 1989 | Issued |
Array
(
[id] => 2686872
[patent_doc_number] => 05049518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'Method of making a trench dram cell'
[patent_app_type] => 1
[patent_app_number] => 7/450515
[patent_app_country] => US
[patent_app_date] => 1989-12-14
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2574
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[pdf_file] => patents/05/049/05049518.pdf
[firstpage_image] =>[orig_patent_app_number] => 450515
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/450515 | Method of making a trench dram cell | Dec 13, 1989 | Issued |
Array
(
[id] => 2747386
[patent_doc_number] => 05037772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-06
[patent_title] => 'Method for forming a polysilicon to polysilicon capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/450334
[patent_app_country] => US
[patent_app_date] => 1989-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 2799
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[pdf_file] => patents/05/037/05037772.pdf
[firstpage_image] =>[orig_patent_app_number] => 450334
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/450334 | Method for forming a polysilicon to polysilicon capacitor | Dec 12, 1989 | Issued |
Array
(
[id] => 2713135
[patent_doc_number] => 05053352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-01
[patent_title] => 'Method of forming an integrated circuit with pn-junction capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/447849
[patent_app_country] => US
[patent_app_date] => 1989-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/053/05053352.pdf
[firstpage_image] =>[orig_patent_app_number] => 447849
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/447849 | Method of forming an integrated circuit with pn-junction capacitor | Dec 7, 1989 | Issued |
Array
(
[id] => 2732827
[patent_doc_number] => 05032533
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-16
[patent_title] => 'Method of making a nonvolatile memory cell with field-plate switch'
[patent_app_type] => 1
[patent_app_number] => 7/444585
[patent_app_country] => US
[patent_app_date] => 1989-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/032/05032533.pdf
[firstpage_image] =>[orig_patent_app_number] => 444585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/444585 | Method of making a nonvolatile memory cell with field-plate switch | Dec 3, 1989 | Issued |
Array
(
[id] => 2734602
[patent_doc_number] => 05077228
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Process for simultaneous formation of trench contact and vertical transistor gate and structure'
[patent_app_type] => 1
[patent_app_number] => 7/444508
[patent_app_country] => US
[patent_app_date] => 1989-12-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/077/05077228.pdf
[firstpage_image] =>[orig_patent_app_number] => 444508
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/444508 | Process for simultaneous formation of trench contact and vertical transistor gate and structure | Nov 30, 1989 | Issued |
Array
(
[id] => 2824646
[patent_doc_number] => 05116776
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-26
[patent_title] => 'Method of making a stacked copacitor for DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 7/443897
[patent_app_country] => US
[patent_app_date] => 1989-11-30
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[pdf_file] => patents/05/116/05116776.pdf
[firstpage_image] =>[orig_patent_app_number] => 443897
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/443897 | Method of making a stacked copacitor for DRAM cell | Nov 29, 1989 | Issued |
Array
(
[id] => 2656242
[patent_doc_number] => 04971921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-20
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 7/440213
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[pdf_file] => patents/04/971/04971921.pdf
[firstpage_image] =>[orig_patent_app_number] => 440213
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/440213 | Semiconductor device and method of manufacturing the same | Nov 21, 1989 | Issued |
Array
(
[id] => 2644885
[patent_doc_number] => 04980308
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[patent_kind] => NA
[patent_issue_date] => 1990-12-25
[patent_title] => 'Method of making a thin film transistor'
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[patent_app_number] => 7/433449
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[patent_app_date] => 1989-11-13
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[pdf_file] => patents/04/980/04980308.pdf
[firstpage_image] =>[orig_patent_app_number] => 433449
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/433449 | Method of making a thin film transistor | Nov 12, 1989 | Issued |
Array
(
[id] => 2624222
[patent_doc_number] => 04950619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-21
[patent_title] => 'Method for the fabrication of a high resistance load resistor utilizing side wall polysilicon spacers'
[patent_app_type] => 1
[patent_app_number] => 7/434241
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[pdf_file] => patents/04/950/04950619.pdf
[firstpage_image] =>[orig_patent_app_number] => 434241
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/434241 | Method for the fabrication of a high resistance load resistor utilizing side wall polysilicon spacers | Nov 12, 1989 | Issued |
Array
(
[id] => 2834349
[patent_doc_number] => 05120674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-09
[patent_title] => 'Method of making stacked capacitor DRAM cell'
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[patent_app_number] => 7/431790
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[pdf_file] => patents/05/120/05120674.pdf
[firstpage_image] =>[orig_patent_app_number] => 431790
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/431790 | Method of making stacked capacitor DRAM cell | Nov 5, 1989 | Issued |
Array
(
[id] => 2632339
[patent_doc_number] => 04977099
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-11
[patent_title] => 'Method for fabricating semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/430691
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[pdf_file] => patents/04/977/04977099.pdf
[firstpage_image] =>[orig_patent_app_number] => 430691
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/430691 | Method for fabricating semiconductor memory device | Oct 30, 1989 | Issued |
Array
(
[id] => 2709292
[patent_doc_number] => 05061651
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[patent_kind] => NA
[patent_issue_date] => 1991-10-29
[patent_title] => 'Method of making dram cell with stacked capacitor'
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[pdf_file] => patents/05/061/05061651.pdf
[firstpage_image] =>[orig_patent_app_number] => 428045
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/428045 | Method of making dram cell with stacked capacitor | Oct 26, 1989 | Issued |