Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3694560 [patent_doc_number] => 05661062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Ultra high density, non-volatile ferromagnetic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/430048 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 6424 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661062.pdf [firstpage_image] =>[orig_patent_app_number] => 430048 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430048
Ultra high density, non-volatile ferromagnetic random access memory Apr 26, 1995 Issued
08/429602 PROCESS FOR FABRICATING A STACKED CAPACITOR Apr 26, 1995 Abandoned
Array ( [id] => 3624929 [patent_doc_number] => 05620916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method for improving via/contact coverage in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/428393 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3743 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620916.pdf [firstpage_image] =>[orig_patent_app_number] => 428393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/428393
Method for improving via/contact coverage in an integrated circuit Apr 23, 1995 Issued
Array ( [id] => 3538020 [patent_doc_number] => 05494842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Method of programming a CMOS read only memory at the second metal layer in a two-metal process' [patent_app_type] => 1 [patent_app_number] => 8/426356 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6448 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494842.pdf [firstpage_image] =>[orig_patent_app_number] => 426356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426356
Method of programming a CMOS read only memory at the second metal layer in a two-metal process Apr 20, 1995 Issued
Array ( [id] => 3543828 [patent_doc_number] => 05554556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method of making a semiconductor memory device having an increased capacitance of memory cell' [patent_app_type] => 1 [patent_app_number] => 8/423092 [patent_app_country] => US [patent_app_date] => 1995-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5028 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/554/05554556.pdf [firstpage_image] =>[orig_patent_app_number] => 423092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/423092
Method of making a semiconductor memory device having an increased capacitance of memory cell Apr 17, 1995 Issued
Array ( [id] => 3524487 [patent_doc_number] => 05504027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Method for fabricating semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 8/421998 [patent_app_country] => US [patent_app_date] => 1995-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504027.pdf [firstpage_image] =>[orig_patent_app_number] => 421998 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421998
Method for fabricating semiconductor memory devices Apr 13, 1995 Issued
Array ( [id] => 3505006 [patent_doc_number] => 05514614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method for producing quantization functional device utilizing a resonance tunneling effect' [patent_app_type] => 1 [patent_app_number] => 8/421530 [patent_app_country] => US [patent_app_date] => 1995-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 113 [patent_no_of_words] => 19347 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514614.pdf [firstpage_image] =>[orig_patent_app_number] => 421530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421530
Method for producing quantization functional device utilizing a resonance tunneling effect Apr 12, 1995 Issued
Array ( [id] => 3546844 [patent_doc_number] => 05545583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method of making semiconductor trench capacitor cell having a buried strap' [patent_app_type] => 1 [patent_app_number] => 8/421115 [patent_app_country] => US [patent_app_date] => 1995-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4550 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/545/05545583.pdf [firstpage_image] =>[orig_patent_app_number] => 421115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421115
Method of making semiconductor trench capacitor cell having a buried strap Apr 12, 1995 Issued
Array ( [id] => 3556628 [patent_doc_number] => 05501999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Process for formation of capacitor for DRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/420546 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2448 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/501/05501999.pdf [firstpage_image] =>[orig_patent_app_number] => 420546 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/420546
Process for formation of capacitor for DRAM cell Apr 11, 1995 Issued
Array ( [id] => 3581474 [patent_doc_number] => 05580810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method of making a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/416099 [patent_app_country] => US [patent_app_date] => 1995-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3790 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580810.pdf [firstpage_image] =>[orig_patent_app_number] => 416099 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/416099
Method of making a semiconductor memory device Apr 3, 1995 Issued
Array ( [id] => 3419345 [patent_doc_number] => 05478770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Methods for manufacturing a storage electrode of DRAM cells' [patent_app_type] => 1 [patent_app_number] => 8/415330 [patent_app_country] => US [patent_app_date] => 1995-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2065 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 577 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/478/05478770.pdf [firstpage_image] =>[orig_patent_app_number] => 415330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/415330
Methods for manufacturing a storage electrode of DRAM cells Apr 2, 1995 Issued
Array ( [id] => 3580699 [patent_doc_number] => 05498564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction' [patent_app_type] => 1 [patent_app_number] => 8/409790 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3925 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498564.pdf [firstpage_image] =>[orig_patent_app_number] => 409790 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409790
Structure and method for reducing parasitic leakage in a memory array with merged isolation and node trench construction Mar 23, 1995 Issued
08/399844 METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACTS TO A THIN CONDUCTIVE LAYER Mar 6, 1995 Abandoned
Array ( [id] => 3506140 [patent_doc_number] => 05569619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Method for forming a capacitor of a semiconductor memory cell' [patent_app_type] => 1 [patent_app_number] => 8/395260 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/569/05569619.pdf [firstpage_image] =>[orig_patent_app_number] => 395260 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395260
Method for forming a capacitor of a semiconductor memory cell Feb 27, 1995 Issued
Array ( [id] => 3574410 [patent_doc_number] => 05523253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-04 [patent_title] => 'Array protection devices and fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/389529 [patent_app_country] => US [patent_app_date] => 1995-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3516 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/523/05523253.pdf [firstpage_image] =>[orig_patent_app_number] => 389529 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389529
Array protection devices and fabrication method Feb 15, 1995 Issued
Array ( [id] => 3521914 [patent_doc_number] => 05489544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method for making a high capacitance multi-level storage node for high density TFT load SRAMS with low soft error rates' [patent_app_type] => 1 [patent_app_number] => 8/386845 [patent_app_country] => US [patent_app_date] => 1995-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2491 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489544.pdf [firstpage_image] =>[orig_patent_app_number] => 386845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/386845
Method for making a high capacitance multi-level storage node for high density TFT load SRAMS with low soft error rates Feb 9, 1995 Issued
Array ( [id] => 3518960 [patent_doc_number] => 05529944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method of making cross point four square folded bitline trench DRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/383137 [patent_app_country] => US [patent_app_date] => 1995-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2532 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529944.pdf [firstpage_image] =>[orig_patent_app_number] => 383137 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/383137
Method of making cross point four square folded bitline trench DRAM cell Feb 1, 1995 Issued
Array ( [id] => 3589210 [patent_doc_number] => 05496756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Method for forming a nonvolatile memory device' [patent_app_type] => 1 [patent_app_number] => 8/340914 [patent_app_country] => US [patent_app_date] => 1995-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4424 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496756.pdf [firstpage_image] =>[orig_patent_app_number] => 340914 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340914
Method for forming a nonvolatile memory device Jan 29, 1995 Issued
Array ( [id] => 3613278 [patent_doc_number] => 05510288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Buried bit line mask ROM process' [patent_app_type] => 1 [patent_app_number] => 8/375782 [patent_app_country] => US [patent_app_date] => 1995-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510288.pdf [firstpage_image] =>[orig_patent_app_number] => 375782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/375782
Buried bit line mask ROM process Jan 19, 1995 Issued
Array ( [id] => 3647712 [patent_doc_number] => 05639681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Process for eliminating effect of polysilicon stringers in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/372992 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2628 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/639/05639681.pdf [firstpage_image] =>[orig_patent_app_number] => 372992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372992
Process for eliminating effect of polysilicon stringers in semiconductor devices Jan 16, 1995 Issued
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