| Application number | Title of the application | Filing Date | Status |
|---|
| 07/359146 | METHOD FOR MANUFACTURING A SEMICONDUCTOR RANDOM ACCESS MEMORY CELL | May 30, 1989 | Abandoned |
Array
(
[id] => 2587648
[patent_doc_number] => 04927772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-22
[patent_title] => 'Method of making high breakdown voltage semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/358057
[patent_app_country] => US
[patent_app_date] => 1989-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4717
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 520
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/927/04927772.pdf
[firstpage_image] =>[orig_patent_app_number] => 358057
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/358057 | Method of making high breakdown voltage semiconductor device | May 29, 1989 | Issued |
Array
(
[id] => 2733771
[patent_doc_number] => 04997779
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-05
[patent_title] => 'Method of making asymmetrical gate field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 7/357536
[patent_app_country] => US
[patent_app_date] => 1989-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 47
[patent_no_of_words] => 5166
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/997/04997779.pdf
[firstpage_image] =>[orig_patent_app_number] => 357536
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/357536 | Method of making asymmetrical gate field effect transistor | May 25, 1989 | Issued |
| 07/355941 | SPLIT METAL PLATE CAPACITOR AND METHOD FOR MAKING THE SAME | May 22, 1989 | Abandoned |
Array
(
[id] => 2602447
[patent_doc_number] => 04948745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-14
[patent_title] => 'Process for elevated source/drain field effect structure'
[patent_app_type] => 1
[patent_app_number] => 7/353933
[patent_app_country] => US
[patent_app_date] => 1989-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3321
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/948/04948745.pdf
[firstpage_image] =>[orig_patent_app_number] => 353933
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/353933 | Process for elevated source/drain field effect structure | May 21, 1989 | Issued |
Array
(
[id] => 2625477
[patent_doc_number] => 04920062
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-24
[patent_title] => 'Manufacturing method for vertically conductive semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 7/352538
[patent_app_country] => US
[patent_app_date] => 1989-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3459
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/920/04920062.pdf
[firstpage_image] =>[orig_patent_app_number] => 352538
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/352538 | Manufacturing method for vertically conductive semiconductor devices | May 15, 1989 | Issued |
| 07/350822 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | May 11, 1989 | Abandoned |
| 07/349367 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING A SILICON BODY IN WHICH SEMICONDUCTOR REGIONS ARE FORMED BY ION IMPLANTATIONS | May 8, 1989 | Abandoned |
| 07/349221 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME | May 7, 1989 | Abandoned |
Array
(
[id] => 2744898
[patent_doc_number] => 04987087
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-22
[patent_title] => 'Process for manufacturing a thyristor with proton irradiation'
[patent_app_type] => 1
[patent_app_number] => 7/348231
[patent_app_country] => US
[patent_app_date] => 1989-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1721
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/987/04987087.pdf
[firstpage_image] =>[orig_patent_app_number] => 348231
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/348231 | Process for manufacturing a thyristor with proton irradiation | May 4, 1989 | Issued |
Array
(
[id] => 2881997
[patent_doc_number] => 05108942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Master slice integrated circuit having a memory region'
[patent_app_type] => 1
[patent_app_number] => 7/346721
[patent_app_country] => US
[patent_app_date] => 1989-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 6179
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/108/05108942.pdf
[firstpage_image] =>[orig_patent_app_number] => 346721
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/346721 | Master slice integrated circuit having a memory region | May 2, 1989 | Issued |
Array
(
[id] => 2515828
[patent_doc_number] => 04874713
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-17
[patent_title] => 'Method of making asymmetrically optimized CMOS field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 7/345875
[patent_app_country] => US
[patent_app_date] => 1989-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 2803
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/874/04874713.pdf
[firstpage_image] =>[orig_patent_app_number] => 345875
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/345875 | Method of making asymmetrically optimized CMOS field effect transistors | Apr 30, 1989 | Issued |
Array
(
[id] => 2652492
[patent_doc_number] => 05025741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-25
[patent_title] => 'Method of making semiconductor integrated circuit device with polysilicon contacts'
[patent_app_type] => 1
[patent_app_number] => 7/344404
[patent_app_country] => US
[patent_app_date] => 1989-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 9072
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/025/05025741.pdf
[firstpage_image] =>[orig_patent_app_number] => 344404
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/344404 | Method of making semiconductor integrated circuit device with polysilicon contacts | Apr 27, 1989 | Issued |
Array
(
[id] => 2628425
[patent_doc_number] => 04937075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-26
[patent_title] => 'Method of making semiconductor chip having field effect transistors which have differing threshold voltages determined in a single masking step'
[patent_app_type] => 1
[patent_app_number] => 7/343689
[patent_app_country] => US
[patent_app_date] => 1989-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2751
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/937/04937075.pdf
[firstpage_image] =>[orig_patent_app_number] => 343689
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/343689 | Method of making semiconductor chip having field effect transistors which have differing threshold voltages determined in a single masking step | Apr 26, 1989 | Issued |
Array
(
[id] => 2626277
[patent_doc_number] => 04906590
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Method of forming a trench capacitor on a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 7/342070
[patent_app_country] => US
[patent_app_date] => 1989-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 2230
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/906/04906590.pdf
[firstpage_image] =>[orig_patent_app_number] => 342070
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/342070 | Method of forming a trench capacitor on a semiconductor substrate | Apr 23, 1989 | Issued |
Array
(
[id] => 2708104
[patent_doc_number] => 05017504
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Vertical type MOS transistor and method of formation thereof'
[patent_app_type] => 1
[patent_app_number] => 7/341596
[patent_app_country] => US
[patent_app_date] => 1989-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 3148
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/017/05017504.pdf
[firstpage_image] =>[orig_patent_app_number] => 341596
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/341596 | Vertical type MOS transistor and method of formation thereof | Apr 20, 1989 | Issued |
| 07/340543 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF PRODUCING THE SAME USING MASTER SLICE APPROACH | Apr 18, 1989 | Abandoned |
Array
(
[id] => 2636197
[patent_doc_number] => 04914043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-04-03
[patent_title] => 'Method of making an integrated light-triggered and light-quenched static induction thyristor'
[patent_app_type] => 1
[patent_app_number] => 7/338271
[patent_app_country] => US
[patent_app_date] => 1989-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 7703
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 399
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/914/04914043.pdf
[firstpage_image] =>[orig_patent_app_number] => 338271
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/338271 | Method of making an integrated light-triggered and light-quenched static induction thyristor | Apr 13, 1989 | Issued |
Array
(
[id] => 2804736
[patent_doc_number] => 05156981
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Method of making a semiconductor device of a high withstand voltage'
[patent_app_type] => 1
[patent_app_number] => 7/334257
[patent_app_country] => US
[patent_app_date] => 1989-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 39
[patent_no_of_words] => 6315
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/156/05156981.pdf
[firstpage_image] =>[orig_patent_app_number] => 334257
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/334257 | Method of making a semiconductor device of a high withstand voltage | Apr 5, 1989 | Issued |
| 07/332879 | PROGRAMMABLE AND ERASABLE MOS MEMORY DEVICE AND FABRICATION PROCESS THEREFOR | Apr 2, 1989 | Abandoned |