Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2723075 [patent_doc_number] => 05057448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Method of making a semiconductor device having DRAM cells and floating gate memory cells' [patent_app_type] => 1 [patent_app_number] => 7/308700 [patent_app_country] => US [patent_app_date] => 1989-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 35 [patent_no_of_words] => 18108 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057448.pdf [firstpage_image] =>[orig_patent_app_number] => 308700 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/308700
Method of making a semiconductor device having DRAM cells and floating gate memory cells Feb 9, 1989 Issued
Array ( [id] => 2666626 [patent_doc_number] => 04904615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-27 [patent_title] => 'Method of making a read only memory device' [patent_app_type] => 1 [patent_app_number] => 7/301978 [patent_app_country] => US [patent_app_date] => 1989-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7288 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/904/04904615.pdf [firstpage_image] =>[orig_patent_app_number] => 301978 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/301978
Method of making a read only memory device Jan 25, 1989 Issued
Array ( [id] => 2522969 [patent_doc_number] => 04877748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Bipolar process for forming shallow NPN emitters' [patent_app_type] => 1 [patent_app_number] => 7/301220 [patent_app_country] => US [patent_app_date] => 1989-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5028 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/877/04877748.pdf [firstpage_image] =>[orig_patent_app_number] => 301220 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/301220
Bipolar process for forming shallow NPN emitters Jan 23, 1989 Issued
Array ( [id] => 2624177 [patent_doc_number] => 04950617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/296307 [patent_app_country] => US [patent_app_date] => 1989-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 3856 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/950/04950617.pdf [firstpage_image] =>[orig_patent_app_number] => 296307 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/296307
Method of manufacturing semiconductor device Jan 11, 1989 Issued
Array ( [id] => 2607255 [patent_doc_number] => 04902636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-20 [patent_title] => 'Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device' [patent_app_type] => 1 [patent_app_number] => 7/294787 [patent_app_country] => US [patent_app_date] => 1989-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2918 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/902/04902636.pdf [firstpage_image] =>[orig_patent_app_number] => 294787 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/294787
Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device Jan 8, 1989 Issued
Array ( [id] => 2883859 [patent_doc_number] => 05268321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'Method of making DRAM cell having improved radiation protection' [patent_app_type] => 1 [patent_app_number] => 7/295101 [patent_app_country] => US [patent_app_date] => 1989-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3573 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/268/05268321.pdf [firstpage_image] =>[orig_patent_app_number] => 295101 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/295101
Method of making DRAM cell having improved radiation protection Jan 8, 1989 Issued
07/290619 BURIED SILICIDED BITLINES Dec 26, 1988 Abandoned
Array ( [id] => 2626202 [patent_doc_number] => 04906586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-06 [patent_title] => 'Suspended gate field effect semiconductor pressure transducer device' [patent_app_type] => 1 [patent_app_number] => 7/290447 [patent_app_country] => US [patent_app_date] => 1988-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3692 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/906/04906586.pdf [firstpage_image] =>[orig_patent_app_number] => 290447 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/290447
Suspended gate field effect semiconductor pressure transducer device Dec 26, 1988 Issued
Array ( [id] => 2596248 [patent_doc_number] => 04965215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip' [patent_app_type] => 1 [patent_app_number] => 7/287067 [patent_app_country] => US [patent_app_date] => 1988-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2933 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965215.pdf [firstpage_image] =>[orig_patent_app_number] => 287067 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/287067
Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip Dec 20, 1988 Issued
Array ( [id] => 2592593 [patent_doc_number] => 04933298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-12 [patent_title] => 'Method of making high speed semiconductor device having a silicon-on-insulator structure' [patent_app_type] => 1 [patent_app_number] => 7/286290 [patent_app_country] => US [patent_app_date] => 1988-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3626 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/933/04933298.pdf [firstpage_image] =>[orig_patent_app_number] => 286290 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/286290
Method of making high speed semiconductor device having a silicon-on-insulator structure Dec 18, 1988 Issued
07/286068 SINGLE POLYSILICON, CROSS-COUPLED RESISTOR, SIX-TRANSISTOR SRAM CELL DESIGN TECHNIQUE Dec 18, 1988 Abandoned
Array ( [id] => 2743189 [patent_doc_number] => 05011788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Process of manufacturing semiconductor integrated circuit device and product formed thereby' [patent_app_type] => 1 [patent_app_number] => 7/284557 [patent_app_country] => US [patent_app_date] => 1988-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 33 [patent_no_of_words] => 5845 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/011/05011788.pdf [firstpage_image] =>[orig_patent_app_number] => 284557 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/284557
Process of manufacturing semiconductor integrated circuit device and product formed thereby Dec 14, 1988 Issued
Array ( [id] => 2714394 [patent_doc_number] => 05008212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-16 [patent_title] => 'Selective asperity definition technique suitable for use in fabricating floating-gate transistor' [patent_app_type] => 1 [patent_app_number] => 7/283340 [patent_app_country] => US [patent_app_date] => 1988-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 29 [patent_no_of_words] => 5917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/008/05008212.pdf [firstpage_image] =>[orig_patent_app_number] => 283340 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/283340
Selective asperity definition technique suitable for use in fabricating floating-gate transistor Dec 11, 1988 Issued
Array ( [id] => 2747867 [patent_doc_number] => 05030586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-09 [patent_title] => 'Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors' [patent_app_type] => 1 [patent_app_number] => 7/282803 [patent_app_country] => US [patent_app_date] => 1988-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3519 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/030/05030586.pdf [firstpage_image] =>[orig_patent_app_number] => 282803 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/282803
Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors Dec 11, 1988 Issued
Array ( [id] => 2636341 [patent_doc_number] => 04914051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Method for making a vertical power DMOS transistor with small signal bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 7/281593 [patent_app_country] => US [patent_app_date] => 1988-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3762 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914051.pdf [firstpage_image] =>[orig_patent_app_number] => 281593 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/281593
Method for making a vertical power DMOS transistor with small signal bipolar transistors Dec 8, 1988 Issued
Array ( [id] => 2656297 [patent_doc_number] => 04971924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Metal plate capacitor and method for making the same' [patent_app_type] => 1 [patent_app_number] => 7/282173 [patent_app_country] => US [patent_app_date] => 1988-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3974 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/971/04971924.pdf [firstpage_image] =>[orig_patent_app_number] => 282173 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/282173
Metal plate capacitor and method for making the same Dec 8, 1988 Issued
Array ( [id] => 2600846 [patent_doc_number] => 04931406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-05 [patent_title] => 'Method for manufacturing semiconductor devices having twin wells' [patent_app_type] => 1 [patent_app_number] => 7/282138 [patent_app_country] => US [patent_app_date] => 1988-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2022 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/931/04931406.pdf [firstpage_image] =>[orig_patent_app_number] => 282138 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/282138
Method for manufacturing semiconductor devices having twin wells Dec 8, 1988 Issued
Array ( [id] => 2596042 [patent_doc_number] => 04921816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Method of making a trench dram' [patent_app_type] => 1 [patent_app_number] => 7/281998 [patent_app_country] => US [patent_app_date] => 1988-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2004 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/921/04921816.pdf [firstpage_image] =>[orig_patent_app_number] => 281998 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/281998
Method of making a trench dram Dec 8, 1988 Issued
Array ( [id] => 2714308 [patent_doc_number] => 05008208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-16 [patent_title] => 'Method of making planarized, self-aligned bipolar integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/281195 [patent_app_country] => US [patent_app_date] => 1988-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/008/05008208.pdf [firstpage_image] =>[orig_patent_app_number] => 281195 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/281195
Method of making planarized, self-aligned bipolar integrated circuits Dec 6, 1988 Issued
Array ( [id] => 2632115 [patent_doc_number] => 04957877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Process for simultaneously fabricating EEPROM cell and flash EPROM cell' [patent_app_type] => 1 [patent_app_number] => 7/274420 [patent_app_country] => US [patent_app_date] => 1988-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4361 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/957/04957877.pdf [firstpage_image] =>[orig_patent_app_number] => 274420 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/274420
Process for simultaneously fabricating EEPROM cell and flash EPROM cell Nov 20, 1988 Issued
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