| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05057448
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Method of making a semiconductor device having DRAM cells and floating gate memory cells'
[patent_app_type] => 1
[patent_app_number] => 7/308700
[patent_app_country] => US
[patent_app_date] => 1989-02-10
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Array
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[patent_doc_number] => 04904615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-27
[patent_title] => 'Method of making a read only memory device'
[patent_app_type] => 1
[patent_app_number] => 7/301978
[patent_app_country] => US
[patent_app_date] => 1989-01-26
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[pdf_file] => patents/04/904/04904615.pdf
[firstpage_image] =>[orig_patent_app_number] => 301978
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/301978 | Method of making a read only memory device | Jan 25, 1989 | Issued |
Array
(
[id] => 2522969
[patent_doc_number] => 04877748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-31
[patent_title] => 'Bipolar process for forming shallow NPN emitters'
[patent_app_type] => 1
[patent_app_number] => 7/301220
[patent_app_country] => US
[patent_app_date] => 1989-01-24
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[pdf_file] => patents/04/877/04877748.pdf
[firstpage_image] =>[orig_patent_app_number] => 301220
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/301220 | Bipolar process for forming shallow NPN emitters | Jan 23, 1989 | Issued |
Array
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[patent_doc_number] => 04950617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-08-21
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/296307
[patent_app_country] => US
[patent_app_date] => 1989-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/04/950/04950617.pdf
[firstpage_image] =>[orig_patent_app_number] => 296307
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/296307 | Method of manufacturing semiconductor device | Jan 11, 1989 | Issued |
Array
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[patent_doc_number] => 04902636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-20
[patent_title] => 'Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device'
[patent_app_type] => 1
[patent_app_number] => 7/294787
[patent_app_country] => US
[patent_app_date] => 1989-01-09
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[firstpage_image] =>[orig_patent_app_number] => 294787
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/294787 | Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device | Jan 8, 1989 | Issued |
Array
(
[id] => 2883859
[patent_doc_number] => 05268321
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-07
[patent_title] => 'Method of making DRAM cell having improved radiation protection'
[patent_app_type] => 1
[patent_app_number] => 7/295101
[patent_app_country] => US
[patent_app_date] => 1989-01-09
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[firstpage_image] =>[orig_patent_app_number] => 295101
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/295101 | Method of making DRAM cell having improved radiation protection | Jan 8, 1989 | Issued |
| 07/290619 | BURIED SILICIDED BITLINES | Dec 26, 1988 | Abandoned |
Array
(
[id] => 2626202
[patent_doc_number] => 04906586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-03-06
[patent_title] => 'Suspended gate field effect semiconductor pressure transducer device'
[patent_app_type] => 1
[patent_app_number] => 7/290447
[patent_app_country] => US
[patent_app_date] => 1988-12-27
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[pdf_file] => patents/04/906/04906586.pdf
[firstpage_image] =>[orig_patent_app_number] => 290447
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/290447 | Suspended gate field effect semiconductor pressure transducer device | Dec 26, 1988 | Issued |
Array
(
[id] => 2596248
[patent_doc_number] => 04965215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-10-23
[patent_title] => 'Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip'
[patent_app_type] => 1
[patent_app_number] => 7/287067
[patent_app_country] => US
[patent_app_date] => 1988-12-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/965/04965215.pdf
[firstpage_image] =>[orig_patent_app_number] => 287067
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/287067 | Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip | Dec 20, 1988 | Issued |
Array
(
[id] => 2592593
[patent_doc_number] => 04933298
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-12
[patent_title] => 'Method of making high speed semiconductor device having a silicon-on-insulator structure'
[patent_app_type] => 1
[patent_app_number] => 7/286290
[patent_app_country] => US
[patent_app_date] => 1988-12-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/933/04933298.pdf
[firstpage_image] =>[orig_patent_app_number] => 286290
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/286290 | Method of making high speed semiconductor device having a silicon-on-insulator structure | Dec 18, 1988 | Issued |
| 07/286068 | SINGLE POLYSILICON, CROSS-COUPLED RESISTOR, SIX-TRANSISTOR SRAM CELL DESIGN TECHNIQUE | Dec 18, 1988 | Abandoned |
Array
(
[id] => 2743189
[patent_doc_number] => 05011788
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Process of manufacturing semiconductor integrated circuit device and product formed thereby'
[patent_app_type] => 1
[patent_app_number] => 7/284557
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[patent_app_date] => 1988-12-15
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[pdf_file] => patents/05/011/05011788.pdf
[firstpage_image] =>[orig_patent_app_number] => 284557
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/284557 | Process of manufacturing semiconductor integrated circuit device and product formed thereby | Dec 14, 1988 | Issued |
Array
(
[id] => 2714394
[patent_doc_number] => 05008212
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-16
[patent_title] => 'Selective asperity definition technique suitable for use in fabricating floating-gate transistor'
[patent_app_type] => 1
[patent_app_number] => 7/283340
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[patent_app_date] => 1988-12-12
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[pdf_file] => patents/05/008/05008212.pdf
[firstpage_image] =>[orig_patent_app_number] => 283340
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/283340 | Selective asperity definition technique suitable for use in fabricating floating-gate transistor | Dec 11, 1988 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors'
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Array
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[patent_doc_number] => 04914051
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[patent_issue_date] => 1990-04-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/281593 | Method for making a vertical power DMOS transistor with small signal bipolar transistors | Dec 8, 1988 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1990-11-20
[patent_title] => 'Metal plate capacitor and method for making the same'
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[patent_app_number] => 7/282173
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[patent_app_date] => 1988-12-09
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[firstpage_image] =>[orig_patent_app_number] => 282173
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/282173 | Metal plate capacitor and method for making the same | Dec 8, 1988 | Issued |
Array
(
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[patent_doc_number] => 04931406
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[patent_kind] => NA
[patent_issue_date] => 1990-06-05
[patent_title] => 'Method for manufacturing semiconductor devices having twin wells'
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[pdf_file] => patents/04/931/04931406.pdf
[firstpage_image] =>[orig_patent_app_number] => 282138
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/282138 | Method for manufacturing semiconductor devices having twin wells | Dec 8, 1988 | Issued |
Array
(
[id] => 2596042
[patent_doc_number] => 04921816
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[patent_kind] => NA
[patent_issue_date] => 1990-05-01
[patent_title] => 'Method of making a trench dram'
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[patent_app_number] => 7/281998
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[firstpage_image] =>[orig_patent_app_number] => 281998
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/281998 | Method of making a trench dram | Dec 8, 1988 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1991-04-16
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[firstpage_image] =>[orig_patent_app_number] => 281195
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/281195 | Method of making planarized, self-aligned bipolar integrated circuits | Dec 6, 1988 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/274420 | Process for simultaneously fabricating EEPROM cell and flash EPROM cell | Nov 20, 1988 | Issued |