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Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
07/274164 METHOD OF MAKING CROSSPOINT DYNAMIC RAM CELL ARRAY WITH OVERLAPRING WORDLINES AND FOLDED BITLINES Nov 20, 1988 Abandoned
Array ( [id] => 2655174 [patent_doc_number] => 04929563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-29 [patent_title] => 'Method of manufacturing semiconductor device with overvoltage self-protection' [patent_app_type] => 1 [patent_app_number] => 7/272842 [patent_app_country] => US [patent_app_date] => 1988-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3576 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/929/04929563.pdf [firstpage_image] =>[orig_patent_app_number] => 272842 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/272842
Method of manufacturing semiconductor device with overvoltage self-protection Nov 17, 1988 Issued
Array ( [id] => 2630852 [patent_doc_number] => 04937202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Method of manufacturing field effect transistors having self-registering source and drain regions to minimize capacitances' [patent_app_type] => 1 [patent_app_number] => 7/272660 [patent_app_country] => US [patent_app_date] => 1988-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4234 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937202.pdf [firstpage_image] =>[orig_patent_app_number] => 272660 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/272660
Method of manufacturing field effect transistors having self-registering source and drain regions to minimize capacitances Nov 16, 1988 Issued
Array ( [id] => 2524056 [patent_doc_number] => 04873202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Solid state relay and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/268215 [patent_app_country] => US [patent_app_date] => 1988-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 5018 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873202.pdf [firstpage_image] =>[orig_patent_app_number] => 268215 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/268215
Solid state relay and method of manufacturing the same Nov 6, 1988 Issued
Array ( [id] => 2560995 [patent_doc_number] => 04857478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Method of manufacturing a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/267374 [patent_app_country] => US [patent_app_date] => 1988-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4188 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/857/04857478.pdf [firstpage_image] =>[orig_patent_app_number] => 267374 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/267374
Method of manufacturing a semiconductor memory device Nov 3, 1988 Issued
Array ( [id] => 2644839 [patent_doc_number] => 04980306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-25 [patent_title] => 'Method of making a CMOS device with trench isolation device' [patent_app_type] => 1 [patent_app_number] => 7/265698 [patent_app_country] => US [patent_app_date] => 1988-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2383 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/980/04980306.pdf [firstpage_image] =>[orig_patent_app_number] => 265698 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/265698
Method of making a CMOS device with trench isolation device Oct 31, 1988 Issued
07/265306 DEFECT FREE TRENCH ISOLATION DEVICES AND METHOD OF FABRICATION Oct 24, 1988 Abandoned
Array ( [id] => 2767361 [patent_doc_number] => 05036021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Method of producing a semiconductor device with total dielectric isolation' [patent_app_type] => 1 [patent_app_number] => 7/259558 [patent_app_country] => US [patent_app_date] => 1988-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3598 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036021.pdf [firstpage_image] =>[orig_patent_app_number] => 259558 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/259558
Method of producing a semiconductor device with total dielectric isolation Oct 17, 1988 Issued
07/259521 MASTER SLICE TYPE INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF Oct 12, 1988 Abandoned
Array ( [id] => 2635540 [patent_doc_number] => 04898835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-06 [patent_title] => 'Single mask totally self-aligned power MOSFET cell fabrication process' [patent_app_type] => 1 [patent_app_number] => 7/256505 [patent_app_country] => US [patent_app_date] => 1988-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2618 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/898/04898835.pdf [firstpage_image] =>[orig_patent_app_number] => 256505 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/256505
Single mask totally self-aligned power MOSFET cell fabrication process Oct 11, 1988 Issued
Array ( [id] => 2523017 [patent_doc_number] => 04877750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Method of fabricating a trench capacitor cell for a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/254836 [patent_app_country] => US [patent_app_date] => 1988-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2780 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/877/04877750.pdf [firstpage_image] =>[orig_patent_app_number] => 254836 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/254836
Method of fabricating a trench capacitor cell for a semiconductor memory device Oct 6, 1988 Issued
Array ( [id] => 2623781 [patent_doc_number] => 04956310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Semiconductor memory device and fabricating method thereof' [patent_app_type] => 1 [patent_app_number] => 7/195672 [patent_app_country] => US [patent_app_date] => 1988-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1807 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956310.pdf [firstpage_image] =>[orig_patent_app_number] => 195672 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/195672
Semiconductor memory device and fabricating method thereof Oct 4, 1988 Issued
Array ( [id] => 2624240 [patent_doc_number] => 04950620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Process for making integrated circuit with doped silicon dioxide load elements' [patent_app_type] => 1 [patent_app_number] => 7/252268 [patent_app_country] => US [patent_app_date] => 1988-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7457 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/950/04950620.pdf [firstpage_image] =>[orig_patent_app_number] => 252268 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/252268
Process for making integrated circuit with doped silicon dioxide load elements Sep 29, 1988 Issued
07/265798 METHOD OF MAKING A THIN FILM TRANSISTOR Sep 29, 1988 Abandoned
Array ( [id] => 2600938 [patent_doc_number] => 04912052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-27 [patent_title] => 'Method of testing semiconductor elements' [patent_app_type] => 1 [patent_app_number] => 7/248137 [patent_app_country] => US [patent_app_date] => 1988-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4995 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/912/04912052.pdf [firstpage_image] =>[orig_patent_app_number] => 248137 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/248137
Method of testing semiconductor elements Sep 22, 1988 Issued
Array ( [id] => 2686764 [patent_doc_number] => 05049512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Method of forming a MOS field-effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/247625 [patent_app_country] => US [patent_app_date] => 1988-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 2769 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/049/05049512.pdf [firstpage_image] =>[orig_patent_app_number] => 247625 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/247625
Method of forming a MOS field-effect transistor Sep 21, 1988 Issued
07/242990 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME Sep 11, 1988 Abandoned
07/241972 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE Sep 7, 1988 Abandoned
Array ( [id] => 2475708 [patent_doc_number] => 04889822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-26 [patent_title] => 'Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities' [patent_app_type] => 1 [patent_app_number] => 7/241269 [patent_app_country] => US [patent_app_date] => 1988-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1995 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/889/04889822.pdf [firstpage_image] =>[orig_patent_app_number] => 241269 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/241269
Manufacturing process for a monolithic integrated semiconductor device having multiple epitaxial layers with a low concentration of impurities Sep 6, 1988 Issued
07/239288 METHOD OF MANUFACTURING SUPERCONDUCTING PATTERNS Aug 31, 1988 Abandoned
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