
Tom Thomas
Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2893, 2899, 2811 |
| Total Applications | 746 |
| Issued Applications | 628 |
| Pending Applications | 6 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2561014
[patent_doc_number] => 04857479
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-15
[patent_title] => 'Method of making poly-sidewall contact transistors'
[patent_app_type] => 1
[patent_app_number] => 7/191923
[patent_app_country] => US
[patent_app_date] => 1988-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 22
[patent_no_of_words] => 7512
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 462
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/857/04857479.pdf
[firstpage_image] =>[orig_patent_app_number] => 191923
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/191923 | Method of making poly-sidewall contact transistors | May 8, 1988 | Issued |
Array
(
[id] => 2666509
[patent_doc_number] => 04904609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-27
[patent_title] => 'Method of making symmetrical blocking high voltage breakdown semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/190903
[patent_app_country] => US
[patent_app_date] => 1988-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4442
[patent_no_of_claims] => 13
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[patent_words_short_claim] => 156
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/904/04904609.pdf
[firstpage_image] =>[orig_patent_app_number] => 190903
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/190903 | Method of making symmetrical blocking high voltage breakdown semiconductor device | May 5, 1988 | Issued |
Array
(
[id] => 2475822
[patent_doc_number] => 04871688
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-03
[patent_title] => 'Sequence of etching polysilicon in semiconductor memory devices'
[patent_app_type] => 1
[patent_app_number] => 7/189412
[patent_app_country] => US
[patent_app_date] => 1988-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3253
[patent_no_of_claims] => 6
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/871/04871688.pdf
[firstpage_image] =>[orig_patent_app_number] => 189412
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/189412 | Sequence of etching polysilicon in semiconductor memory devices | May 1, 1988 | Issued |
Array
(
[id] => 2632132
[patent_doc_number] => 04957878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-18
[patent_title] => 'Reduced mask manufacture of semiconductor memory devices'
[patent_app_type] => 1
[patent_app_number] => 7/189411
[patent_app_country] => US
[patent_app_date] => 1988-05-02
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3255
[patent_no_of_claims] => 3
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[pdf_file] => patents/04/957/04957878.pdf
[firstpage_image] =>[orig_patent_app_number] => 189411
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/189411 | Reduced mask manufacture of semiconductor memory devices | May 1, 1988 | Issued |
Array
(
[id] => 2490255
[patent_doc_number] => 04829014
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-09
[patent_title] => 'Screenable power chip mosaics, a method for fabricating large power semiconductor chips'
[patent_app_type] => 1
[patent_app_number] => 7/189254
[patent_app_country] => US
[patent_app_date] => 1988-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4547
[patent_no_of_claims] => 11
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[pdf_file] => patents/04/829/04829014.pdf
[firstpage_image] =>[orig_patent_app_number] => 189254
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/189254 | Screenable power chip mosaics, a method for fabricating large power semiconductor chips | May 1, 1988 | Issued |
Array
(
[id] => 2490518
[patent_doc_number] => 04824804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-04-25
[patent_title] => 'Method of making vertical enhancement-mode group III-V compound MISFETS'
[patent_app_type] => 1
[patent_app_number] => 7/187606
[patent_app_country] => US
[patent_app_date] => 1988-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/04/824/04824804.pdf
[firstpage_image] =>[orig_patent_app_number] => 187606
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/187606 | Method of making vertical enhancement-mode group III-V compound MISFETS | Apr 27, 1988 | Issued |
Array
(
[id] => 2479335
[patent_doc_number] => 04882289
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-11-21
[patent_title] => 'Method of making a semiconductor memory device with recessed array region'
[patent_app_type] => 1
[patent_app_number] => 7/184786
[patent_app_country] => US
[patent_app_date] => 1988-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 30
[patent_no_of_words] => 15976
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/882/04882289.pdf
[firstpage_image] =>[orig_patent_app_number] => 184786
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/184786 | Method of making a semiconductor memory device with recessed array region | Apr 21, 1988 | Issued |
| 07/181740 | METHOD FOR CONNECTING AN ELECTRONIC COMPONENT FOR TESTING AND MOUNTING IT, AND DEVICE FOR THE IMPLEMENTATION OF THIS METHOD | Apr 13, 1988 | Abandoned |
Array
(
[id] => 2490427
[patent_doc_number] => 04824799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-04-25
[patent_title] => 'Method of making a bipolar semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/178875
[patent_app_country] => US
[patent_app_date] => 1988-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3337
[patent_no_of_claims] => 6
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[pdf_file] => patents/04/824/04824799.pdf
[firstpage_image] =>[orig_patent_app_number] => 178875
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/178875 | Method of making a bipolar semiconductor device | Apr 3, 1988 | Issued |
Array
(
[id] => 2528571
[patent_doc_number] => 04839306
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-13
[patent_title] => 'Method of manufacturing a trench filled with an insulating material in a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 7/174453
[patent_app_country] => US
[patent_app_date] => 1988-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/04/839/04839306.pdf
[firstpage_image] =>[orig_patent_app_number] => 174453
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/174453 | Method of manufacturing a trench filled with an insulating material in a semiconductor substrate | Mar 22, 1988 | Issued |
| 07/170614 | SEMICONDUCTOR DIODE AND METHOD FOR MAKING IT | Mar 10, 1988 | Abandoned |
Array
(
[id] => 2523035
[patent_doc_number] => 04877751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-31
[patent_title] => 'Method of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implant'
[patent_app_type] => 1
[patent_app_number] => 7/166973
[patent_app_country] => US
[patent_app_date] => 1988-03-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/877/04877751.pdf
[firstpage_image] =>[orig_patent_app_number] => 166973
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/166973 | Method of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implant | Mar 10, 1988 | Issued |
Array
(
[id] => 2616321
[patent_doc_number] => 04943538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-07-24
[patent_title] => 'Programmable low impedance anti-fuse element'
[patent_app_type] => 1
[patent_app_number] => 7/166324
[patent_app_country] => US
[patent_app_date] => 1988-03-10
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[firstpage_image] =>[orig_patent_app_number] => 166324
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/166324 | Programmable low impedance anti-fuse element | Mar 9, 1988 | Issued |
Array
(
[id] => 2787353
[patent_doc_number] => 05100823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'Method of making buried stacked transistor-capacitor'
[patent_app_type] => 1
[patent_app_number] => 7/161925
[patent_app_country] => US
[patent_app_date] => 1988-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/100/05100823.pdf
[firstpage_image] =>[orig_patent_app_number] => 161925
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/161925 | Method of making buried stacked transistor-capacitor | Feb 28, 1988 | Issued |
Array
(
[id] => 2553666
[patent_doc_number] => 04803172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Method of manufacturing thyristor with integrated power supply for an associated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/163199
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[patent_app_date] => 1988-02-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/803/04803172.pdf
[firstpage_image] =>[orig_patent_app_number] => 163199
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/163199 | Method of manufacturing thyristor with integrated power supply for an associated circuit | Feb 25, 1988 | Issued |
Array
(
[id] => 2420118
[patent_doc_number] => 04788158
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[patent_issue_date] => 1988-11-29
[patent_title] => 'Method of making vertical inverter'
[patent_app_type] => 1
[patent_app_number] => 7/156128
[patent_app_country] => US
[patent_app_date] => 1988-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 156128
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/156128 | Method of making vertical inverter | Feb 15, 1988 | Issued |
Array
(
[id] => 2742510
[patent_doc_number] => 05023194
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[patent_issue_date] => 1991-06-11
[patent_title] => 'Method of making a multicollector vertical pnp transistor'
[patent_app_type] => 1
[patent_app_number] => 7/154832
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[firstpage_image] =>[orig_patent_app_number] => 154832
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/154832 | Method of making a multicollector vertical pnp transistor | Feb 10, 1988 | Issued |
Array
(
[id] => 2525470
[patent_doc_number] => 04861731
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-29
[patent_title] => 'Method of fabricating a lateral dual gate thyristor'
[patent_app_type] => 1
[patent_app_number] => 7/151534
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[patent_app_date] => 1988-02-02
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[pdf_file] => patents/04/861/04861731.pdf
[firstpage_image] =>[orig_patent_app_number] => 151534
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/151534 | Method of fabricating a lateral dual gate thyristor | Feb 1, 1988 | Issued |
Array
(
[id] => 2488507
[patent_doc_number] => 04859621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-22
[patent_title] => 'Method for setting the threshold voltage of a vertical power MOSFET'
[patent_app_type] => 1
[patent_app_number] => 7/150755
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[patent_app_date] => 1988-02-01
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[pdf_file] => patents/04/859/04859621.pdf
[firstpage_image] =>[orig_patent_app_number] => 150755
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/150755 | Method for setting the threshold voltage of a vertical power MOSFET | Jan 31, 1988 | Issued |
Array
(
[id] => 2515117
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[patent_issue_date] => 1989-08-08
[patent_title] => 'Test method for random defects in electronic microstructures'
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[patent_app_number] => 7/149809
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[pdf_file] => patents/04/855/04855253.pdf
[firstpage_image] =>[orig_patent_app_number] => 149809
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/149809 | Test method for random defects in electronic microstructures | Jan 28, 1988 | Issued |