
Tom Thomas
Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2893, 2899, 2811 |
| Total Applications | 746 |
| Issued Applications | 628 |
| Pending Applications | 6 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2508251
[patent_doc_number] => 04830977
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-16
[patent_title] => 'Method of making a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/148956
[patent_app_country] => US
[patent_app_date] => 1988-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3789
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 268
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/830/04830977.pdf
[firstpage_image] =>[orig_patent_app_number] => 148956
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/148956 | Method of making a semiconductor memory device | Jan 26, 1988 | Issued |
Array
(
[id] => 2508337
[patent_doc_number] => 04830981
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-05-16
[patent_title] => 'Trench capacitor process for high density dynamic ram'
[patent_app_type] => 1
[patent_app_number] => 7/147381
[patent_app_country] => US
[patent_app_date] => 1988-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 1843
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[patent_words_short_claim] => 267
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/830/04830981.pdf
[firstpage_image] =>[orig_patent_app_number] => 147381
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/147381 | Trench capacitor process for high density dynamic ram | Jan 24, 1988 | Issued |
Array
(
[id] => 2515890
[patent_doc_number] => 04874716
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-17
[patent_title] => 'Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface'
[patent_app_type] => 1
[patent_app_number] => 7/146936
[patent_app_country] => US
[patent_app_date] => 1988-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2690
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/874/04874716.pdf
[firstpage_image] =>[orig_patent_app_number] => 146936
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/146936 | Process for fabricating integrated circuit structure with extremely smooth polysilicone dielectric interface | Jan 21, 1988 | Issued |
| 07/145076 | METHOD OF MANUFACTURING A POLYSILICON EMITTER AND A POLYSILICON GATE USING THE SAME ETCH OF POLYSILICON ON A THIN GATE OXIDE | Jan 18, 1988 | Abandoned |
Array
(
[id] => 2561854
[patent_doc_number] => 04849366
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Method of making a gated isolated structure'
[patent_app_type] => 1
[patent_app_number] => 7/144272
[patent_app_country] => US
[patent_app_date] => 1988-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2783
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[firstpage_image] =>[orig_patent_app_number] => 144272
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/144272 | Method of making a gated isolated structure | Jan 14, 1988 | Issued |
Array
(
[id] => 2515026
[patent_doc_number] => 04855248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-08
[patent_title] => 'Method of making a semiconductor ROM device'
[patent_app_type] => 1
[patent_app_number] => 7/143068
[patent_app_country] => US
[patent_app_date] => 1988-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3440
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[pdf_file] => patents/04/855/04855248.pdf
[firstpage_image] =>[orig_patent_app_number] => 143068
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/143068 | Method of making a semiconductor ROM device | Jan 11, 1988 | Issued |
Array
(
[id] => 2559677
[patent_doc_number] => 04837177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-06
[patent_title] => 'Method of making bipolar semiconductor device having a conductive recombination layer'
[patent_app_type] => 1
[patent_app_number] => 7/138262
[patent_app_country] => US
[patent_app_date] => 1987-12-28
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2214
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[pdf_file] => patents/04/837/04837177.pdf
[firstpage_image] =>[orig_patent_app_number] => 138262
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/138262 | Method of making bipolar semiconductor device having a conductive recombination layer | Dec 27, 1987 | Issued |
Array
(
[id] => 2557711
[patent_doc_number] => 04853348
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-08-01
[patent_title] => 'Process for manufacture of a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/137298
[patent_app_country] => US
[patent_app_date] => 1987-12-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 1734
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[pdf_file] => patents/04/853/04853348.pdf
[firstpage_image] =>[orig_patent_app_number] => 137298
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/137298 | Process for manufacture of a semiconductor memory device | Dec 21, 1987 | Issued |
Array
(
[id] => 2666588
[patent_doc_number] => 04904613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-02-27
[patent_title] => 'Method of manufacturing a DMOS device'
[patent_app_type] => 1
[patent_app_number] => 7/135880
[patent_app_country] => US
[patent_app_date] => 1987-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 7446
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[pdf_file] => patents/04/904/04904613.pdf
[firstpage_image] =>[orig_patent_app_number] => 135880
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/135880 | Method of manufacturing a DMOS device | Dec 20, 1987 | Issued |
Array
(
[id] => 2561927
[patent_doc_number] => 04849370
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-07-18
[patent_title] => 'Anodizable strain layer for SOI semiconductor structures'
[patent_app_type] => 1
[patent_app_number] => 7/136225
[patent_app_country] => US
[patent_app_date] => 1987-12-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/04/849/04849370.pdf
[firstpage_image] =>[orig_patent_app_number] => 136225
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/136225 | Anodizable strain layer for SOI semiconductor structures | Dec 20, 1987 | Issued |
Array
(
[id] => 2553761
[patent_doc_number] => 04803177
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Method of forming interconnections and crossings between metallization levels of an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/135879
[patent_app_country] => US
[patent_app_date] => 1987-12-21
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 135879
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/135879 | Method of forming interconnections and crossings between metallization levels of an integrated circuit | Dec 20, 1987 | Issued |
Array
(
[id] => 2528534
[patent_doc_number] => 04839304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-06-13
[patent_title] => 'Method of making a field effect transistor with overlay gate structure'
[patent_app_type] => 1
[patent_app_number] => 7/134123
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[patent_app_date] => 1987-12-17
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[pdf_file] => patents/04/839/04839304.pdf
[firstpage_image] =>[orig_patent_app_number] => 134123
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/134123 | Method of making a field effect transistor with overlay gate structure | Dec 16, 1987 | Issued |
Array
(
[id] => 2546091
[patent_doc_number] => 04804634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-14
[patent_title] => 'Integrated circuit lateral transistor structure'
[patent_app_type] => 1
[patent_app_number] => 7/132689
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[patent_app_date] => 1987-12-14
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[pdf_file] => patents/04/804/04804634.pdf
[firstpage_image] =>[orig_patent_app_number] => 132689
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/132689 | Integrated circuit lateral transistor structure | Dec 13, 1987 | Issued |
Array
(
[id] => 2553779
[patent_doc_number] => 04803178
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Method of making silicon-on-sapphire gate array'
[patent_app_type] => 1
[patent_app_number] => 7/126562
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[pdf_file] => patents/04/803/04803178.pdf
[firstpage_image] =>[orig_patent_app_number] => 126562
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/126562 | Method of making silicon-on-sapphire gate array | Nov 29, 1987 | Issued |
Array
(
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[patent_doc_number] => 05039620
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[patent_issue_date] => 1991-08-13
[patent_title] => 'Method of making a photoelectric conversion device with a high response speed'
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[patent_app_number] => 7/124566
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[patent_app_date] => 1987-11-24
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[pdf_file] => patents/05/039/05039620.pdf
[firstpage_image] =>[orig_patent_app_number] => 124566
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/124566 | Method of making a photoelectric conversion device with a high response speed | Nov 23, 1987 | Issued |
Array
(
[id] => 2553701
[patent_doc_number] => 04803174
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-07
[patent_title] => 'Bipolar transistor integrated circuit and method of manufacturing the same'
[patent_app_type] => 1
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[pdf_file] => patents/04/803/04803174.pdf
[firstpage_image] =>[orig_patent_app_number] => 121912
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/121912 | Bipolar transistor integrated circuit and method of manufacturing the same | Nov 16, 1987 | Issued |
Array
(
[id] => 2388681
[patent_doc_number] => 04794091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1988-12-27
[patent_title] => 'Method of making high-performance dram arrays including trench capacitors'
[patent_app_type] => 1
[patent_app_number] => 7/121556
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/794/04794091.pdf
[firstpage_image] =>[orig_patent_app_number] => 121556
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/121556 | Method of making high-performance dram arrays including trench capacitors | Nov 16, 1987 | Issued |
Array
(
[id] => 2478141
[patent_doc_number] => 04876220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-24
[patent_title] => 'Method of making programmable low impedance interconnect diode element'
[patent_app_type] => 1
[patent_app_number] => 7/104404
[patent_app_country] => US
[patent_app_date] => 1987-11-13
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[pdf_file] => patents/04/876/04876220.pdf
[firstpage_image] =>[orig_patent_app_number] => 104404
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/104404 | Method of making programmable low impedance interconnect diode element | Nov 12, 1987 | Issued |
Array
(
[id] => 2526158
[patent_doc_number] => 04797373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-01-10
[patent_title] => 'Method of making dRAM cell with trench capacitor'
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[pdf_file] => patents/04/797/04797373.pdf
[firstpage_image] =>[orig_patent_app_number] => 122560
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/122560 | Method of making dRAM cell with trench capacitor | Nov 11, 1987 | Issued |
Array
(
[id] => 2490301
[patent_doc_number] => 04824793
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[patent_issue_date] => 1989-04-25
[patent_title] => 'Method of making DRAM cell with trench capacitor'
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[pdf_file] => patents/04/824/04824793.pdf
[firstpage_image] =>[orig_patent_app_number] => 122559
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/122559 | Method of making DRAM cell with trench capacitor | Nov 11, 1987 | Issued |