Search

Tom Thomas

Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2893, 2899, 2811
Total Applications
746
Issued Applications
628
Pending Applications
6
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
07/117523 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Nov 5, 1987 Abandoned
Array ( [id] => 2528618 [patent_doc_number] => 04839308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-13 [patent_title] => 'Method of making an external-coupled-cavity diode laser' [patent_app_type] => 1 [patent_app_number] => 7/114922 [patent_app_country] => US [patent_app_date] => 1987-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2603 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/839/04839308.pdf [firstpage_image] =>[orig_patent_app_number] => 114922 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/114922
Method of making an external-coupled-cavity diode laser Oct 29, 1987 Issued
Array ( [id] => 2465566 [patent_doc_number] => 04845051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-04 [patent_title] => 'Buried gate JFET' [patent_app_type] => 1 [patent_app_number] => 7/115076 [patent_app_country] => US [patent_app_date] => 1987-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 4129 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/845/04845051.pdf [firstpage_image] =>[orig_patent_app_number] => 115076 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/115076
Buried gate JFET Oct 28, 1987 Issued
Array ( [id] => 2515485 [patent_doc_number] => 04818716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-04 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 7/111690 [patent_app_country] => US [patent_app_date] => 1987-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7263 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/818/04818716.pdf [firstpage_image] =>[orig_patent_app_number] => 111690 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/111690
Semiconductor device and manufacturing method thereof Oct 21, 1987 Issued
Array ( [id] => 2634787 [patent_doc_number] => 04892839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-09 [patent_title] => 'Method of manufacturing a semiconductor device with polysilicon resistors and field plate' [patent_app_type] => 1 [patent_app_number] => 7/109533 [patent_app_country] => US [patent_app_date] => 1987-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 946 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/892/04892839.pdf [firstpage_image] =>[orig_patent_app_number] => 109533 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/109533
Method of manufacturing a semiconductor device with polysilicon resistors and field plate Oct 18, 1987 Issued
07/110638 DEFECT FREE TRENCH ISOLATION DEVICES AND METHOD OF FABRICATION Oct 13, 1987 Abandoned
Array ( [id] => 2782152 [patent_doc_number] => 05164325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Method of making a vertical current flow field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/107725 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 8877 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/164/05164325.pdf [firstpage_image] =>[orig_patent_app_number] => 107725 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/107725
Method of making a vertical current flow field effect transistor Oct 7, 1987 Issued
Array ( [id] => 2491143 [patent_doc_number] => 04843026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-27 [patent_title] => 'Architecture modification for improved ROM security' [patent_app_type] => 1 [patent_app_number] => 7/101206 [patent_app_country] => US [patent_app_date] => 1987-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3403 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/843/04843026.pdf [firstpage_image] =>[orig_patent_app_number] => 101206 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/101206
Architecture modification for improved ROM security Sep 23, 1987 Issued
Array ( [id] => 2560976 [patent_doc_number] => 04857477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'Process for fabricating a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/095147 [patent_app_country] => US [patent_app_date] => 1987-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 1063 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/857/04857477.pdf [firstpage_image] =>[orig_patent_app_number] => 095147 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/095147
Process for fabricating a semiconductor device Sep 10, 1987 Issued
Array ( [id] => 2559712 [patent_doc_number] => 04837179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-06-06 [patent_title] => 'Method of making a LDD mosfet' [patent_app_type] => 1 [patent_app_number] => 7/088108 [patent_app_country] => US [patent_app_date] => 1987-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1049 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/837/04837179.pdf [firstpage_image] =>[orig_patent_app_number] => 088108 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/088108
Method of making a LDD mosfet Aug 30, 1987 Issued
Array ( [id] => 2465474 [patent_doc_number] => 04845046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-04 [patent_title] => 'Process for producing semiconductor devices by self-alignment technology' [patent_app_type] => 1 [patent_app_number] => 7/091609 [patent_app_country] => US [patent_app_date] => 1987-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 22 [patent_no_of_words] => 2745 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/845/04845046.pdf [firstpage_image] =>[orig_patent_app_number] => 091609 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/091609
Process for producing semiconductor devices by self-alignment technology Aug 30, 1987 Issued
Array ( [id] => 2561909 [patent_doc_number] => 04849369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-18 [patent_title] => 'Method of making an EPROM memory cell' [patent_app_type] => 1 [patent_app_number] => 7/087460 [patent_app_country] => US [patent_app_date] => 1987-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 11362 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/849/04849369.pdf [firstpage_image] =>[orig_patent_app_number] => 087460 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/087460
Method of making an EPROM memory cell Aug 19, 1987 Issued
Array ( [id] => 2551008 [patent_doc_number] => 04814287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/082212 [patent_app_country] => US [patent_app_date] => 1987-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3179 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/814/04814287.pdf [firstpage_image] =>[orig_patent_app_number] => 082212 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/082212
Method of manufacturing a semiconductor integrated circuit device Aug 5, 1987 Issued
07/078752 METHOD FOR FABRICATING ISOLATION REGION IN SEMICONDUCTOR DEVICES Jul 27, 1987 Abandoned
Array ( [id] => 2551025 [patent_doc_number] => 04814288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Method of fabricating semiconductor devices which include vertical elements and control elements' [patent_app_type] => 1 [patent_app_number] => 7/072164 [patent_app_country] => US [patent_app_date] => 1987-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 6931 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/814/04814288.pdf [firstpage_image] =>[orig_patent_app_number] => 072164 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/072164
Method of fabricating semiconductor devices which include vertical elements and control elements Jul 9, 1987 Issued
Array ( [id] => 2553685 [patent_doc_number] => 04803173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-07 [patent_title] => 'Method of fabrication of semiconductor device having a planar configuration' [patent_app_type] => 1 [patent_app_number] => 7/067032 [patent_app_country] => US [patent_app_date] => 1987-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/803/04803173.pdf [firstpage_image] =>[orig_patent_app_number] => 067032 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/067032
Method of fabrication of semiconductor device having a planar configuration Jun 28, 1987 Issued
07/063110 METHOD OF PRODUCING SEMICONDUCTOR MEMORY DEVICE Jun 16, 1987 Abandoned
Array ( [id] => 2486124 [patent_doc_number] => 04800175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-24 [patent_title] => 'Phosphorous planar dopant source for low temperature applications' [patent_app_type] => 1 [patent_app_number] => 7/056621 [patent_app_country] => US [patent_app_date] => 1987-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2924 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/800/04800175.pdf [firstpage_image] =>[orig_patent_app_number] => 056621 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/056621
Phosphorous planar dopant source for low temperature applications May 28, 1987 Issued
Array ( [id] => 2555661 [patent_doc_number] => 04816423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Bicmos process for forming shallow npn emitters and mosfet source/drains' [patent_app_type] => 1 [patent_app_number] => 7/045978 [patent_app_country] => US [patent_app_date] => 1987-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5037 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/816/04816423.pdf [firstpage_image] =>[orig_patent_app_number] => 045978 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/045978
Bicmos process for forming shallow npn emitters and mosfet source/drains Apr 30, 1987 Issued
Array ( [id] => 2443886 [patent_doc_number] => 04792530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-20 [patent_title] => 'Process for balancing forward and reverse characteristic of thyristors' [patent_app_type] => 1 [patent_app_number] => 7/032483 [patent_app_country] => US [patent_app_date] => 1987-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1541 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/792/04792530.pdf [firstpage_image] =>[orig_patent_app_number] => 032483 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/032483
Process for balancing forward and reverse characteristic of thyristors Mar 29, 1987 Issued
Menu