Tom Thomas

Array ( [id] => 3613210 [patent_doc_number] => 05510283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Method of making a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/327718 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3558 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510283.pdf [firstpage_image] =>[orig_patent_app_number] => 327718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633503 [patent_doc_number] => 05631182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method of making a semiconductor memory circuit device' [patent_app_type] => 1 [patent_app_number] => 8/327861 [patent_app_country] => US [patent_app_date] => 1994-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631182.pdf [firstpage_image] =>[orig_patent_app_number] => 327861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621331 [patent_doc_number] => 05593912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'SOI trench DRAM cell for 256 MB DRAM and beyond' [patent_app_type] => 1 [patent_app_number] => 8/319833 [patent_app_country] => US [patent_app_date] => 1994-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1211 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593912.pdf [firstpage_image] =>[orig_patent_app_number] => 319833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3554634 [patent_doc_number] => 05543344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method of making programmable read-only memory' [patent_app_type] => 1 [patent_app_number] => 8/318474 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2166 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543344.pdf [firstpage_image] =>[orig_patent_app_number] => 318474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3416693 [patent_doc_number] => 05453393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Method for forming a high density EEPROM cell array with improved access time' [patent_app_type] => 1 [patent_app_number] => 8/318363 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 8278 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 496 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/453/05453393.pdf [firstpage_image] =>[orig_patent_app_number] => 318363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3515052 [patent_doc_number] => 05576223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Method of defect determination and defect engineering on product wafer of advanced submicron technologies' [patent_app_type] => 1 [patent_app_number] => 8/317148 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5828 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576223.pdf [firstpage_image] =>[orig_patent_app_number] => 317148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3440868 [patent_doc_number] => 05429971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Method of making single bit erase flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 8/317016 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3724 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/429/05429971.pdf [firstpage_image] =>[orig_patent_app_number] => 317016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3441969 [patent_doc_number] => 05466624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Isolation between diffusion lines in a memory array' [patent_app_type] => 1 [patent_app_number] => 8/315876 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/466/05466624.pdf [firstpage_image] =>[orig_patent_app_number] => 315876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3419321 [patent_doc_number] => 05478768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Method of manufacturing a semiconductor memory device having improved hold characteristic of a storage capacitor' [patent_app_type] => 1 [patent_app_number] => 8/315850 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4728 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/478/05478768.pdf [firstpage_image] =>[orig_patent_app_number] => 315850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3552928 [patent_doc_number] => 05518944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'MOS transistor and its fabricating method' [patent_app_type] => 1 [patent_app_number] => 8/308756 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6249 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/518/05518944.pdf [firstpage_image] =>[orig_patent_app_number] => 308756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447948 [patent_doc_number] => 05424235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/306434 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 4673 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424235.pdf [firstpage_image] =>[orig_patent_app_number] => 306434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3585976 [patent_doc_number] => 05552333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method for designing low profile variable width input/output cells' [patent_app_type] => 1 [patent_app_number] => 8/307942 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3208 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552333.pdf [firstpage_image] =>[orig_patent_app_number] => 307942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3580003 [patent_doc_number] => 05491105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'LDMOS transistor with self-aligned source/backgate and photo-aligned gate' [patent_app_type] => 1 [patent_app_number] => 8/303792 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 4997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491105.pdf [firstpage_image] =>[orig_patent_app_number] => 303792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3425242 [patent_doc_number] => 05416037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Method of making a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/299885 [patent_app_country] => US [patent_app_date] => 1994-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 7707 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416037.pdf [firstpage_image] =>[orig_patent_app_number] => 299885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3487041 [patent_doc_number] => 05426066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Late programming mask ROM and process for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/298338 [patent_app_country] => US [patent_app_date] => 1994-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 3296 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426066.pdf [firstpage_image] =>[orig_patent_app_number] => 298338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112198 [patent_doc_number] => 05464791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Method of fabricating a micro-trench storage capacitor' [patent_app_type] => 1 [patent_app_number] => 8/297964 [patent_app_country] => US [patent_app_date] => 1994-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 8065 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/464/05464791.pdf [firstpage_image] =>[orig_patent_app_number] => 297964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3476031 [patent_doc_number] => 05432102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Method of making thin film transistor with channel and drain adjacent sidewall of gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/296172 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 2588 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432102.pdf [firstpage_image] =>[orig_patent_app_number] => 296172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3441955 [patent_doc_number] => 05466623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Method of making semiconductor integrated circuit having isolation oxide regions with different thickness' [patent_app_type] => 1 [patent_app_number] => 8/296940 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5182 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/466/05466623.pdf [firstpage_image] =>[orig_patent_app_number] => 296940 [rel_patent_id] =>[rel_patent_doc_number] =>)