
Tom Thomas
Supervisory Patent Examiner (ID: 10930, Phone: (571)272-1664 , Office: P/2893 )
| Most Active Art Unit | 1104 |
| Art Unit(s) | 1104, 2893, 2899, 2811 |
| Total Applications | 746 |
| Issued Applications | 628 |
| Pending Applications | 6 |
| Abandoned Applications | 112 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3412336
[patent_doc_number] => 05444010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Method for forming a stacked capacitor in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/242398
[patent_app_country] => US
[patent_app_date] => 1994-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1073
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 330
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/444/05444010.pdf
[firstpage_image] =>[orig_patent_app_number] => 242398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/242398 | Method for forming a stacked capacitor in a semiconductor device | May 12, 1994 | Issued |
Array
(
[id] => 3421956
[patent_doc_number] => 05389567
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-14
[patent_title] => 'Method of forming a non-volatile DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 8/241136
[patent_app_country] => US
[patent_app_date] => 1994-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 5495
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/389/05389567.pdf
[firstpage_image] =>[orig_patent_app_number] => 241136
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/241136 | Method of forming a non-volatile DRAM cell | May 9, 1994 | Issued |
Array
(
[id] => 3109135
[patent_doc_number] => 05413944
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Twin tub CMOS process'
[patent_app_type] => 1
[patent_app_number] => 8/239426
[patent_app_country] => US
[patent_app_date] => 1994-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 1770
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/413/05413944.pdf
[firstpage_image] =>[orig_patent_app_number] => 239426
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/239426 | Twin tub CMOS process | May 5, 1994 | Issued |
Array
(
[id] => 3117421
[patent_doc_number] => 05380673
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-10
[patent_title] => 'Dram capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 8/239130
[patent_app_country] => US
[patent_app_date] => 1994-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5330
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 374
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/380/05380673.pdf
[firstpage_image] =>[orig_patent_app_number] => 239130
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/239130 | Dram capacitor structure | May 5, 1994 | Issued |
Array
(
[id] => 3446200
[patent_doc_number] => 05387534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-07
[patent_title] => 'Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/238474
[patent_app_country] => US
[patent_app_date] => 1994-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 2936
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/387/05387534.pdf
[firstpage_image] =>[orig_patent_app_number] => 238474
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/238474 | Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells | May 4, 1994 | Issued |
Array
(
[id] => 3537981
[patent_doc_number] => 05494839
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Dual photo-resist process for fabricating high density DRAM'
[patent_app_type] => 1
[patent_app_number] => 8/237352
[patent_app_country] => US
[patent_app_date] => 1994-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1430
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/494/05494839.pdf
[firstpage_image] =>[orig_patent_app_number] => 237352
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/237352 | Dual photo-resist process for fabricating high density DRAM | May 2, 1994 | Issued |
Array
(
[id] => 3410979
[patent_doc_number] => 05411905
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-02
[patent_title] => 'Method of making trench EEPROM structure on SOI with dual channels'
[patent_app_type] => 1
[patent_app_number] => 8/236752
[patent_app_country] => US
[patent_app_date] => 1994-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2705
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/411/05411905.pdf
[firstpage_image] =>[orig_patent_app_number] => 236752
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/236752 | Method of making trench EEPROM structure on SOI with dual channels | Apr 28, 1994 | Issued |
Array
(
[id] => 3580653
[patent_doc_number] => 05498562
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Semiconductor processing methods of forming stacked capacitors'
[patent_app_type] => 1
[patent_app_number] => 8/237371
[patent_app_country] => US
[patent_app_date] => 1994-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 4561
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 583
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/498/05498562.pdf
[firstpage_image] =>[orig_patent_app_number] => 237371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/237371 | Semiconductor processing methods of forming stacked capacitors | Apr 28, 1994 | Issued |
Array
(
[id] => 3423774
[patent_doc_number] => 05459095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-17
[patent_title] => 'Method for making capacitor for use in DRAM cell using triple layers of photoresist'
[patent_app_type] => 1
[patent_app_number] => 8/233646
[patent_app_country] => US
[patent_app_date] => 1994-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 1977
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/459/05459095.pdf
[firstpage_image] =>[orig_patent_app_number] => 233646
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/233646 | Method for making capacitor for use in DRAM cell using triple layers of photoresist | Apr 25, 1994 | Issued |
Array
(
[id] => 3122950
[patent_doc_number] => 05436188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'Dram cell process having elk horn shaped capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/233766
[patent_app_country] => US
[patent_app_date] => 1994-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2918
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/436/05436188.pdf
[firstpage_image] =>[orig_patent_app_number] => 233766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/233766 | Dram cell process having elk horn shaped capacitor | Apr 25, 1994 | Issued |
Array
(
[id] => 3424732
[patent_doc_number] => 05422296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Process for forming a static-random-access memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/232968
[patent_app_country] => US
[patent_app_date] => 1994-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4968
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 336
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/422/05422296.pdf
[firstpage_image] =>[orig_patent_app_number] => 232968
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/232968 | Process for forming a static-random-access memory cell | Apr 24, 1994 | Issued |
Array
(
[id] => 3122906
[patent_doc_number] => 05436186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'Process for fabricating a stacked capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/231516
[patent_app_country] => US
[patent_app_date] => 1994-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 4227
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 343
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/436/05436186.pdf
[firstpage_image] =>[orig_patent_app_number] => 231516
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/231516 | Process for fabricating a stacked capacitor | Apr 21, 1994 | Issued |
| 08/228536 | METHOD FOR FORMING A STRONG DIELECTRIC FILM BY THE SOL-GEL TECHNIQUE AND A METHOD FOR MANUFACTURING A CAPACITOR | Apr 14, 1994 | Abandoned |
Array
(
[id] => 3453909
[patent_doc_number] => 05378649
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas'
[patent_app_type] => 1
[patent_app_number] => 8/224696
[patent_app_country] => US
[patent_app_date] => 1994-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2610
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/378/05378649.pdf
[firstpage_image] =>[orig_patent_app_number] => 224696
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/224696 | Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas | Apr 7, 1994 | Issued |
Array
(
[id] => 3111983
[patent_doc_number] => 05395777
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-07
[patent_title] => 'Method of producing VDMOS transistors'
[patent_app_type] => 1
[patent_app_number] => 8/223596
[patent_app_country] => US
[patent_app_date] => 1994-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 1500
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/395/05395777.pdf
[firstpage_image] =>[orig_patent_app_number] => 223596
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223596 | Method of producing VDMOS transistors | Apr 5, 1994 | Issued |
Array
(
[id] => 3444504
[patent_doc_number] => 05397726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Segment-erasable flash EPROM'
[patent_app_type] => 1
[patent_app_number] => 8/217076
[patent_app_country] => US
[patent_app_date] => 1994-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 3185
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 434
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397726.pdf
[firstpage_image] =>[orig_patent_app_number] => 217076
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/217076 | Segment-erasable flash EPROM | Mar 24, 1994 | Issued |
Array
(
[id] => 2993882
[patent_doc_number] => 05362666
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-08
[patent_title] => 'Method of producing a self-aligned contact penetrating cell plate'
[patent_app_type] => 1
[patent_app_number] => 8/213381
[patent_app_country] => US
[patent_app_date] => 1994-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 8352
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/362/05362666.pdf
[firstpage_image] =>[orig_patent_app_number] => 213381
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/213381 | Method of producing a self-aligned contact penetrating cell plate | Mar 14, 1994 | Issued |
Array
(
[id] => 3411092
[patent_doc_number] => 05411912
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-02
[patent_title] => 'Method of making a semiconductor device comprising lower and upper silicon layers as capacitor electrodes'
[patent_app_type] => 1
[patent_app_number] => 8/207200
[patent_app_country] => US
[patent_app_date] => 1994-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 34
[patent_no_of_words] => 7483
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/411/05411912.pdf
[firstpage_image] =>[orig_patent_app_number] => 207200
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/207200 | Method of making a semiconductor device comprising lower and upper silicon layers as capacitor electrodes | Mar 7, 1994 | Issued |
Array
(
[id] => 3036942
[patent_doc_number] => 05372966
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-13
[patent_title] => 'Method of making semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/203944
[patent_app_country] => US
[patent_app_date] => 1994-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 3448
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/372/05372966.pdf
[firstpage_image] =>[orig_patent_app_number] => 203944
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/203944 | Method of making semiconductor device | Feb 28, 1994 | Issued |
Array
(
[id] => 3552959
[patent_doc_number] => 05518946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Process for fabricating capacitors in dynamic RAM'
[patent_app_type] => 1
[patent_app_number] => 8/203677
[patent_app_country] => US
[patent_app_date] => 1994-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3894
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/518/05518946.pdf
[firstpage_image] =>[orig_patent_app_number] => 203677
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/203677 | Process for fabricating capacitors in dynamic RAM | Feb 27, 1994 | Issued |