Search

Tomi Sweet Skibinski

Examiner (ID: 5162)

Most Active Art Unit
2842
Art Unit(s)
2842, 2816
Total Applications
1555
Issued Applications
1363
Pending Applications
78
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8889120 [patent_doc_number] => 20130162304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Gate Line Driver Capable Of Controlling Slew Rate Thereof' [patent_app_type] => utility [patent_app_number] => 13/605249 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/605249
Gate Line Driver Capable Of Controlling Slew Rate Thereof Sep 5, 2012 Abandoned
Array ( [id] => 8777869 [patent_doc_number] => 20130099844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'CLOCK DISTRIBUTION CIRCUIT AND METHOD OF FORMING CLOCK DISTRIBUTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/603755 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603755
Clock distribution circuit and method of forming clock distribution circuit Sep 4, 2012 Issued
Array ( [id] => 9335760 [patent_doc_number] => 20140062542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'GATE DRIVER CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/603480 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603480 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/603480
Gate driver circuit and method Sep 4, 2012 Issued
Array ( [id] => 9167503 [patent_doc_number] => 08593186 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Control signal generator for use with a command decoder' [patent_app_type] => utility [patent_app_number] => 13/602025 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2687 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602025 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602025
Control signal generator for use with a command decoder Aug 30, 2012 Issued
Array ( [id] => 9627398 [patent_doc_number] => 08797084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Calibration schemes for charge-recycling stacked voltage domains' [patent_app_type] => utility [patent_app_number] => 13/601240 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13601240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/601240
Calibration schemes for charge-recycling stacked voltage domains Aug 30, 2012 Issued
Array ( [id] => 9335777 [patent_doc_number] => 20140062559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/598513 [patent_app_country] => US [patent_app_date] => 2012-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14955 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13598513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/598513
System and method of adjusting a clock signal Aug 28, 2012 Issued
Array ( [id] => 8681536 [patent_doc_number] => 20130049820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'CLOCK DIVIDER UNIT' [patent_app_type] => utility [patent_app_number] => 13/592994 [patent_app_country] => US [patent_app_date] => 2012-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4934 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/592994
CLOCK DIVIDER UNIT Aug 22, 2012 Abandoned
Array ( [id] => 9402541 [patent_doc_number] => 08692599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Interpolative divider linearity enhancement techniques' [patent_app_type] => utility [patent_app_number] => 13/592160 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 7580 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13592160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/592160
Interpolative divider linearity enhancement techniques Aug 21, 2012 Issued
Array ( [id] => 9316975 [patent_doc_number] => 20140049312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'RF SWITCH WITH COMPLEMENTARY SWITCHING DEVICES' [patent_app_type] => utility [patent_app_number] => 13/588197 [patent_app_country] => US [patent_app_date] => 2012-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3371 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13588197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/588197
RF SWITCH WITH COMPLEMENTARY SWITCHING DEVICES Aug 16, 2012 Abandoned
Array ( [id] => 9300419 [patent_doc_number] => 08648650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Integrated circuit with dynamic power supply control' [patent_app_type] => utility [patent_app_number] => 13/571613 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 60 [patent_no_of_words] => 26013 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571613 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/571613
Integrated circuit with dynamic power supply control Aug 9, 2012 Issued
Array ( [id] => 9274213 [patent_doc_number] => 08638149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Equalized rise and fall slew rates for a buffer' [patent_app_type] => utility [patent_app_number] => 13/567214 [patent_app_country] => US [patent_app_date] => 2012-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13567214 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/567214
Equalized rise and fall slew rates for a buffer Aug 5, 2012 Issued
Array ( [id] => 9141181 [patent_doc_number] => 08581650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Duty cycle correction circuit and delay locked loop circuit including the same' [patent_app_type] => utility [patent_app_number] => 13/563863 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6415 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563863 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563863
Duty cycle correction circuit and delay locked loop circuit including the same Jul 31, 2012 Issued
Array ( [id] => 10871148 [patent_doc_number] => 08896353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method and apparatus for constant output impedance, variable pre-emphasis drive' [patent_app_type] => utility [patent_app_number] => 13/564375 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6166 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564375
Method and apparatus for constant output impedance, variable pre-emphasis drive Jul 31, 2012 Issued
Array ( [id] => 9292028 [patent_doc_number] => 20140035661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'AN INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING LOAD ON THE OUTPUT FROM ON-CHIP VOLTAGE GENERATION CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 13/562516 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12843 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562516 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562516
Integrated circuit and method for controlling load on the output from on-chip voltage generation circuitry Jul 30, 2012 Issued
Array ( [id] => 9292002 [patent_doc_number] => 20140035636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'CLOCK SYNCHRONIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/563530 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563530 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563530
Clock synchronization circuit Jul 30, 2012 Issued
Array ( [id] => 8969453 [patent_doc_number] => 08508271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-13 [patent_title] => 'Phase locked loop' [patent_app_type] => utility [patent_app_number] => 13/562813 [patent_app_country] => US [patent_app_date] => 2012-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7230 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/562813
Phase locked loop Jul 30, 2012 Issued
Array ( [id] => 9278396 [patent_doc_number] => 20140028364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 13/560371 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3971 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13560371 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/560371
CRITICAL PATH MONITOR HARDWARE ARCHITECTURE FOR CLOSED LOOP ADAPTIVE VOLTAGE SCALING AND METHOD OF OPERATION THEREOF Jul 26, 2012 Abandoned
Array ( [id] => 9128038 [patent_doc_number] => 08575989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-05 [patent_title] => 'High isolation switch' [patent_app_type] => utility [patent_app_number] => 13/545774 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6883 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545774
High isolation switch Jul 9, 2012 Issued
Array ( [id] => 9356200 [patent_doc_number] => 08674742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Driver circuit for preventing overshoot and undershoot due to parasitic capacitance' [patent_app_type] => utility [patent_app_number] => 13/538724 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7222 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538724
Driver circuit for preventing overshoot and undershoot due to parasitic capacitance Jun 28, 2012 Issued
Array ( [id] => 10640075 [patent_doc_number] => 09357599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Lighting control circuit, illuminating lamp using the lighting control circuit, and lighting device using the illuminating lamp' [patent_app_type] => utility [patent_app_number] => 14/131037 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3066 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14131037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/131037
Lighting control circuit, illuminating lamp using the lighting control circuit, and lighting device using the illuminating lamp Jun 26, 2012 Issued
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