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Tong-ho Kim

Examiner (ID: 597)

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1280
Issued Applications
1123
Pending Applications
134
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18488581 [patent_doc_number] => 20230215929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => METAL GATE CAP [patent_app_type] => utility [patent_app_number] => 18/182665 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182665
Metal gate cap Mar 12, 2023 Issued
Array ( [id] => 19436155 [patent_doc_number] => 20240304653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => HIGH ABSORPTION STRUCTURE FOR OPTOELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/181982 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181982
High absorption structure for optoelectronic device Mar 9, 2023 Issued
Array ( [id] => 19597097 [patent_doc_number] => 12154951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Germanium tin gate-all-around device [patent_app_type] => utility [patent_app_number] => 18/178893 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178893 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178893
Germanium tin gate-all-around device Mar 5, 2023 Issued
Array ( [id] => 18789634 [patent_doc_number] => 20230378336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/117405 [patent_app_country] => US [patent_app_date] => 2023-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117405 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/117405
Semiconductor device Mar 3, 2023 Issued
Array ( [id] => 20305412 [patent_doc_number] => 12451412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Backside gate via structure using self-aligned scheme [patent_app_type] => utility [patent_app_number] => 18/177171 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 1085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177171 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177171
Backside gate via structure using self-aligned scheme Mar 1, 2023 Issued
Array ( [id] => 19639718 [patent_doc_number] => 12170335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Epitaxial structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/174831 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174831
Epitaxial structures for semiconductor devices Feb 26, 2023 Issued
Array ( [id] => 18496601 [patent_doc_number] => 20230219188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => MEGA-SONIC VIBRATION ASSISTED CHEMICAL MECHANICAL PLANARIZATION [patent_app_type] => utility [patent_app_number] => 18/174125 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174125
Mega-sonic vibration assisted chemical mechanical planarization Feb 23, 2023 Issued
Array ( [id] => 19392957 [patent_doc_number] => 20240282827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => FIELD PLATE BIASING OF HIGH ELECTRON MOBILITY TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/172916 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172916
Field plate biasing of high electron mobility transistor Feb 21, 2023 Issued
Array ( [id] => 19131001 [patent_doc_number] => 20240136354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING STACKED FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/171754 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171754
Integrated circuit devices including stacked field effect transistors and methods of forming the same Feb 20, 2023 Issued
Array ( [id] => 19294680 [patent_doc_number] => 12034045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Semiconductor device structure with nanostructure [patent_app_type] => utility [patent_app_number] => 18/171091 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 43 [patent_no_of_words] => 9483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171091
Semiconductor device structure with nanostructure Feb 16, 2023 Issued
Array ( [id] => 19261063 [patent_doc_number] => 12021130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Circuit structure with gate configuration [patent_app_type] => utility [patent_app_number] => 18/171128 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171128
Circuit structure with gate configuration Feb 16, 2023 Issued
Array ( [id] => 18898819 [patent_doc_number] => 20240014304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/170104 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170104 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170104
Semiconductor device and method for manufacturing the same Feb 15, 2023 Issued
Array ( [id] => 19314544 [patent_doc_number] => 12040371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class [patent_app_type] => utility [patent_app_number] => 18/168338 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 67 [patent_no_of_words] => 9814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168338 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168338
Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class Feb 12, 2023 Issued
Array ( [id] => 19063269 [patent_doc_number] => 11942523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor devices and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/168422 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 55 [patent_no_of_words] => 11724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168422
Semiconductor devices and methods of forming the same Feb 12, 2023 Issued
Array ( [id] => 19055025 [patent_doc_number] => 20240096994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MULTIPLE GATE PATTERNING METHODS TOWARDS FUTURE NANOSHEET SCALING [patent_app_type] => utility [patent_app_number] => 18/167718 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167718
MULTIPLE GATE PATTERNING METHODS TOWARDS FUTURE NANOSHEET SCALING Feb 9, 2023 Pending
Array ( [id] => 18440267 [patent_doc_number] => 20230187562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => TRANSISTOR, INTEGRATED CIRCUIT, AND MANUFACTURING METHOD OF TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/165936 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165936 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165936
Transistor, integrated circuit, and manufacturing method of transistor Feb 7, 2023 Issued
Array ( [id] => 20637891 [patent_doc_number] => 12598787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Field effect transistor with dual layer isolation structure and method [patent_app_type] => utility [patent_app_number] => 18/165853 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 6228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165853
Field effect transistor with dual layer isolation structure and method Feb 6, 2023 Issued
Array ( [id] => 18394976 [patent_doc_number] => 20230163197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 18/158641 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158641
Semiconductor Device and Method of Manufacture Jan 23, 2023 Pending
Array ( [id] => 18848852 [patent_doc_number] => 20230411256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGING MEMBER, SEMICONDUCTOR PACKAGING MEMBER AND MOUNTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/099933 [patent_app_country] => US [patent_app_date] => 2023-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099933
Manufacturing method of semiconductor packaging member, semiconductor packaging member and mounting method thereof Jan 20, 2023 Issued
Array ( [id] => 20332842 [patent_doc_number] => 12463127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Integrated circuit (IC) package employing a re-distribution layer (RDL) substrate(s) with photosensitive dielectric layer(s) for increased package rigidity, and related fabrication methods [patent_app_type] => utility [patent_app_number] => 18/155398 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 44 [patent_no_of_words] => 10152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155398
Integrated circuit (IC) package employing a re-distribution layer (RDL) substrate(s) with photosensitive dielectric layer(s) for increased package rigidity, and related fabrication methods Jan 16, 2023 Issued
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