Search

Tong-ho Kim

Examiner (ID: 14896, Phone: (571)270-0276 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1263
Issued Applications
1115
Pending Applications
128
Abandoned Applications
51

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18991305 [patent_doc_number] => 20240063274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SOURCE OR DRAIN STRUCTURES WITH PHOSPHOROUS AND ARSENIC DOPANTS [patent_app_type] => utility [patent_app_number] => 17/889986 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889986
SOURCE OR DRAIN STRUCTURES WITH PHOSPHOROUS AND ARSENIC DOPANTS Aug 16, 2022 Pending
Array ( [id] => 19314502 [patent_doc_number] => 12040328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor devices including two-dimensional material and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/884772 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 80 [patent_no_of_words] => 11285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884772 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884772
Semiconductor devices including two-dimensional material and methods of fabrication thereof Aug 9, 2022 Issued
Array ( [id] => 19123599 [patent_doc_number] => 11967594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/884840 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 9807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884840
Semiconductor device structure and methods of forming the same Aug 9, 2022 Issued
Array ( [id] => 18040217 [patent_doc_number] => 20220384434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE HAVING NANOSHEET TRANSISTOR AND METHODS OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/883971 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883971 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883971
Semiconductor device having nanosheet transistor and methods of fabrication thereof Aug 8, 2022 Issued
Array ( [id] => 18959035 [patent_doc_number] => 20240047362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Memory Circuitry And Method Used In Forming Memory Circuitry [patent_app_type] => utility [patent_app_number] => 17/881308 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881308
Memory circuitry and method used in forming memory circuitry Aug 3, 2022 Issued
Array ( [id] => 19958480 [patent_doc_number] => 12328911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/878936 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 3222 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878936
Semiconductor device Aug 1, 2022 Issued
Array ( [id] => 19139494 [patent_doc_number] => 11974487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/878067 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 17978 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878067
Display device Jul 31, 2022 Issued
Array ( [id] => 19124811 [patent_doc_number] => 11968819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Gate-all-around field-effect transistors in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/877050 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 14324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877050
Gate-all-around field-effect transistors in integrated circuits Jul 28, 2022 Issued
Array ( [id] => 18008917 [patent_doc_number] => 20220367684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => ISOLATION STRUCTURES IN MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/815913 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815913
Isolation structures in multi-gate semiconductor devices and methods of fabricating the same Jul 27, 2022 Issued
Array ( [id] => 19094066 [patent_doc_number] => 11955533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Ion implantation to reduce nanosheet gate length variation [patent_app_type] => utility [patent_app_number] => 17/873380 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873380
Ion implantation to reduce nanosheet gate length variation Jul 25, 2022 Issued
Array ( [id] => 18255521 [patent_doc_number] => 20230082560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/873575 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873575
Display device Jul 25, 2022 Issued
Array ( [id] => 18874769 [patent_doc_number] => 11862592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Sidewall spacer to reduce bond pad necking and/or redistribution layer necking [patent_app_type] => utility [patent_app_number] => 17/869850 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869850
Sidewall spacer to reduce bond pad necking and/or redistribution layer necking Jul 20, 2022 Issued
Array ( [id] => 19168489 [patent_doc_number] => 11984402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/870531 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 54 [patent_no_of_words] => 15775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870531
Semiconductor device and method Jul 20, 2022 Issued
Array ( [id] => 17993732 [patent_doc_number] => 20220359769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => LIGHTLY-DOPED CHANNEL EXTENSIONS [patent_app_type] => utility [patent_app_number] => 17/813975 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813975
Lightly-doped channel extensions Jul 20, 2022 Issued
Array ( [id] => 19314580 [patent_doc_number] => 12040407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor devices including backside vias and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/814132 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 89 [patent_no_of_words] => 16667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814132
Semiconductor devices including backside vias and methods of forming the same Jul 20, 2022 Issued
Array ( [id] => 19079560 [patent_doc_number] => 11948940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Multi-gate device structure [patent_app_type] => utility [patent_app_number] => 17/869069 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869069
Multi-gate device structure Jul 19, 2022 Issued
Array ( [id] => 18145836 [patent_doc_number] => 20230019692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => 3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC CHANNEL REGIONS [patent_app_type] => utility [patent_app_number] => 17/866154 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866154
3D hybrid memory using horizontally oriented conductive dielectric channel regions Jul 14, 2022 Issued
Array ( [id] => 17993227 [patent_doc_number] => 20220359264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Methods of Forming Spacers for Semiconductor Devices Including Backside Power Rails [patent_app_type] => utility [patent_app_number] => 17/812902 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812902
Methods of forming spacers for semiconductor devices including backside power rails Jul 14, 2022 Issued
Array ( [id] => 20276488 [patent_doc_number] => 12446277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/859242 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 10503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/859242
Semiconductor device and method of fabricating the same Jul 6, 2022 Issued
Array ( [id] => 17949613 [patent_doc_number] => 20220336632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Gate Patterning Process For Multi-Gate Devices [patent_app_type] => utility [patent_app_number] => 17/858544 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858544
Gate patterning process for multi-gate devices Jul 5, 2022 Issued
Menu