Search

Tong-ho Kim

Examiner (ID: 282, Phone: (571)270-0276 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1305
Issued Applications
1141
Pending Applications
141
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18073776 [patent_doc_number] => 11532617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/134694 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 10199 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134694
Semiconductor structure and method of forming the same Dec 27, 2020 Issued
Array ( [id] => 18001016 [patent_doc_number] => 11502127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 17/135968 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135968
Semiconductor memory devices Dec 27, 2020 Issued
Array ( [id] => 16781966 [patent_doc_number] => 20210119045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SERIES CONNECTED STACKED VERTICAL TRANSISTORS FOR HIGH VOLTAGE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/134632 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134632
Series connected stacked vertical transistors for high voltage applications Dec 27, 2020 Issued
Array ( [id] => 16782024 [patent_doc_number] => 20210119103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => SUPERCONDUCTIVE JUNCTION, SUPERCONDUCTING APPARATUS, METHOD OF MANUFACTURING SUPERCONDUCTING JUNCTION AND CONTROL METHOD OF SUPERCONDUCTING JUNCTION [patent_app_type] => utility [patent_app_number] => 17/247850 [patent_app_country] => US [patent_app_date] => 2020-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247850
Superconductive junction, superconducting apparatus, method of manufacturing superconducting junction and control method of superconducting junction Dec 26, 2020 Issued
Array ( [id] => 16936863 [patent_doc_number] => 20210202752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE HAVING MULTIPLE GATE TERMINALS [patent_app_type] => utility [patent_app_number] => 17/132264 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132264
Semiconductor device structure having multiple gate terminals Dec 22, 2020 Issued
Array ( [id] => 18016515 [patent_doc_number] => 11508823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Low capacitance low RC wrap-around-contact [patent_app_type] => utility [patent_app_number] => 17/132980 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 8149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132980
Low capacitance low RC wrap-around-contact Dec 22, 2020 Issued
Array ( [id] => 16782242 [patent_doc_number] => 20210119321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ANTENNA MODULE [patent_app_type] => utility [patent_app_number] => 17/132224 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132224
Antenna module Dec 22, 2020 Issued
Array ( [id] => 16765644 [patent_doc_number] => 20210111226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MEMORY ARRAY WITH GRADED MEMORY STACK RESISTANCES [patent_app_type] => utility [patent_app_number] => 17/130215 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130215
Memory array with graded memory stack resistances Dec 21, 2020 Issued
Array ( [id] => 17692479 [patent_doc_number] => 20220199772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => NANOSHEET SEMICONDUCTOR DEVICES WITH N/P BOUNDARY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/128351 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128351
Nanosheet semiconductor devices with n/p boundary structure Dec 20, 2020 Issued
Array ( [id] => 16966167 [patent_doc_number] => 20210217666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => METHOD OF MAKING A CONTINUOUS CHANNEL BETWEEN 3D CMOS [patent_app_type] => utility [patent_app_number] => 17/123987 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123987 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123987
Method of making a continuous channel between 3D CMOS Dec 15, 2020 Issued
Array ( [id] => 16936865 [patent_doc_number] => 20210202754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => Thin Film Transistor Comprising Oxide Semiconductor Layer and Silicon Semiconductor Layer and Display Apparatus Comprising the Same [patent_app_type] => utility [patent_app_number] => 17/121248 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121248
Thin film transistor comprising oxide semiconductor layer and silicon semiconductor layer and display apparatus comprising the same Dec 13, 2020 Issued
Array ( [id] => 16796132 [patent_doc_number] => 20210125949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SIDEWALL SPACER TO REDUCE BOND PAD NECKING AND/OR REDISTRIBUTION LAYER NECKING [patent_app_type] => utility [patent_app_number] => 17/117665 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117665
Sidewall spacer to reduce bond pad necking and/or redistribution layer necking Dec 9, 2020 Issued
Array ( [id] => 18105504 [patent_doc_number] => 11545401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Isolated semiconductor layer stacks for a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/114826 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 39 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114826
Isolated semiconductor layer stacks for a semiconductor device Dec 7, 2020 Issued
Array ( [id] => 18048108 [patent_doc_number] => 11522066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Sidewall passivation for HEMT devices [patent_app_type] => utility [patent_app_number] => 17/114715 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114715
Sidewall passivation for HEMT devices Dec 7, 2020 Issued
Array ( [id] => 18032225 [patent_doc_number] => 11515425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Thin film transistor array substrate and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/115582 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13653 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115582 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115582
Thin film transistor array substrate and electronic device including the same Dec 7, 2020 Issued
Array ( [id] => 16781738 [patent_doc_number] => 20210118817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => Dummy Die Placement Without Backside Chipping [patent_app_type] => utility [patent_app_number] => 17/113396 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113396
Dummy die placement without backside chipping Dec 6, 2020 Issued
Array ( [id] => 17956512 [patent_doc_number] => 11482627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/112831 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 7192 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112831
C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same Dec 3, 2020 Issued
Array ( [id] => 16920729 [patent_doc_number] => 20210193821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SELF-ALIGNED CONTACTS FOR WALLED NANOSHEET AND FORKSHEET FIELD EFFECT TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/112844 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112844
Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices Dec 3, 2020 Issued
Array ( [id] => 16782041 [patent_doc_number] => 20210119120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/112861 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112861
Memory device and method for fabricating the same Dec 3, 2020 Issued
Array ( [id] => 18073913 [patent_doc_number] => 11532756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/112903 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 8156 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112903
C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same Dec 3, 2020 Issued
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