Tong-ho Kim

Array ( [id] => 16746662 [patent_doc_number] => 10971667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Light emitting device and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 16/853340 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 9009 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16853340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16617469 [patent_doc_number] => 20210036122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => Methods of Reducing Parasitic Capacitance in Multi-Gate Field-Effect Transistors [patent_app_type] => utility [patent_app_number] => 16/850733 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16617322 [patent_doc_number] => 20210035975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/849238 [patent_app_country] => US [patent_app_date] => 2020-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16849238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16379358 [patent_doc_number] => 20200328201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/837970 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17063126 [patent_doc_number] => 11107736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Gate structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/835987 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 43 [patent_no_of_words] => 9282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17130611 [patent_doc_number] => 20210305380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => DEVICE CONTACTS IN INTEGRATED CIRCUIT STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/832283 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17130482 [patent_doc_number] => 20210305251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => LOW LEAKAGE GATE STACK FOR A TRANSISTOR DEVICE AND METHODS OF MAKING AN IC PRODUCT THAT INCLUDES SUCH A TRANSISTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/832139 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803325 [patent_doc_number] => 10998278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Process and method for achieving high immunity to ultrafast high voltage transients across inorganic galvanic isolation barriers [patent_app_type] => utility [patent_app_number] => 16/832356 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17224852 [patent_doc_number] => 11177362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/829372 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 10729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16181119 [patent_doc_number] => 20200228088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SUBSTRATE FOR A TEMPERATURE-COMPENSATED SURFACE ACOUSTIC WAVE DEVICE OR VOLUME ACOUSTIC WAVE DEVICE [patent_app_type] => utility [patent_app_number] => 16/829604 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17018416 [patent_doc_number] => 11088061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Substrate, semiconductor device package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/814729 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 6510 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17085677 [patent_doc_number] => 20210280684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => TRANSISTOR WITH INSULATOR [patent_app_type] => utility [patent_app_number] => 16/812292 [patent_app_country] => US [patent_app_date] => 2020-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16973702 [patent_doc_number] => 11069684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-20 [patent_title] => Stacked field effect transistors with reduced coupling effect [patent_app_type] => utility [patent_app_number] => 16/809205 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16809205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16553155 [patent_doc_number] => 10886321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Color image-capture element and image capture device [patent_app_type] => utility [patent_app_number] => 16/804393 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 39 [patent_no_of_words] => 10878 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16081123 [patent_doc_number] => 20200194548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/799905 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 420 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16724053 [patent_doc_number] => 20210091200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => TRANSISTOR STRUCTURE WITH OVERLYING GATE ON POLYSILICON GATE STRUCTURE AND RELATED METHOD [patent_app_type] => utility [patent_app_number] => 16/788914 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16417975 [patent_doc_number] => 10825877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Electroluminescence display device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/783297 [patent_app_country] => US [patent_app_date] => 2020-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6040 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16783297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15939563 [patent_doc_number] => 20200161415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => TRENCH CAPACITOR WITH WARPAGE REDUCTION [patent_app_type] => utility [patent_app_number] => 16/774014 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16995600 [patent_doc_number] => 20210234020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => NANOSHEET TRANSISTOR HAVING A STRAINED CHANNEL WITH STRAIN-PRESERVING MULTI-SEGMENTED SOURCE/DRAIN REGIONS [patent_app_type] => utility [patent_app_number] => 16/752900 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17847989 [patent_doc_number] => 11437375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Layout construction for addressing electromigration [patent_app_type] => utility [patent_app_number] => 16/744227 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 12654 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744227 [rel_patent_id] =>[rel_patent_doc_number] =>)