Tong-ho Kim

Array ( [id] => 16249665 [patent_doc_number] => 10749041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Programmable charge storage transistor, an array of elevationally-extending strings of memory cells, methods of forming Si3Nx, methods of forming insulator material that is between a control gate and charge-storage material of a programmable charge-storage transistor, methods of forming an array of elevationally-extending strings of memory cells, a programmable charge-storage transistor manufactured in accordance with methods, and an array of elevationally-extending strings of memory cells man [patent_app_type] => utility [patent_app_number] => 16/659478 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6712 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16638165 [patent_doc_number] => 10916682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Micro light-emitting device and display apparatus [patent_app_type] => utility [patent_app_number] => 16/658174 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7991 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16783629 [patent_doc_number] => 20210120708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MICROELECTRONIC PACKAGE ELECTROSTATIC DISCHARGE (ESD) PROTECTION [patent_app_type] => utility [patent_app_number] => 16/659459 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16789208 [patent_doc_number] => 10991647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Printed circuit board and package structure having the same [patent_app_type] => utility [patent_app_number] => 16/658288 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 8168 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16545030 [patent_doc_number] => 20200411445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SEMICONDUCTOR PACKAGES AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/658131 [patent_app_country] => US [patent_app_date] => 2019-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781803 [patent_doc_number] => 20210118882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => STRUCTURE AND METHOD OF INTEGRATED CIRCUIT HAVING DECOUPLE CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/657699 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781684 [patent_doc_number] => 20210118763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => INTEGRATED CIRCUIT CHIP DEVICE WITH THERMAL CONTROL [patent_app_type] => utility [patent_app_number] => 16/657861 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609387 [patent_doc_number] => 10910402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Three-dimensional and flash memory and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/657810 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5171 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17224711 [patent_doc_number] => 11177221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Semiconductor device package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/657882 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 56 [patent_no_of_words] => 6271 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15503667 [patent_doc_number] => 20200052022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Light Blocking Layer for Image Sensor Device [patent_app_type] => utility [patent_app_number] => 16/657469 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781749 [patent_doc_number] => 20210118828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => ANTENNA APPARATUS WITH INTEGRATED ANTENNA ARRAY AND LOW LOSS MULTI-LAYER INTERPOSER [patent_app_type] => utility [patent_app_number] => 16/655523 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15873595 [patent_doc_number] => 20200144201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => Surface- Mount Thin-Film Components having Terminals Configured for Visual Inspection [patent_app_type] => utility [patent_app_number] => 16/655280 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16668453 [patent_doc_number] => 10937710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Electronic component module [patent_app_type] => utility [patent_app_number] => 16/655331 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4578 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16218663 [patent_doc_number] => 10734486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Lateral high electron mobility transistor with integrated clamp diode [patent_app_type] => utility [patent_app_number] => 16/600041 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5595 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462465 [patent_doc_number] => 20200044057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM [patent_app_type] => utility [patent_app_number] => 16/597428 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15462467 [patent_doc_number] => 20200044058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM [patent_app_type] => utility [patent_app_number] => 16/597502 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15969839 [patent_doc_number] => 20200168671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/596050 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15746059 [patent_doc_number] => 20200111919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => DEVICES INCLUDING VERTICAL TRANSISTORS, AND RELATED METHODS AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/596370 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16789234 [patent_doc_number] => 10991673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 16/591797 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 17089 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15922427 [patent_doc_number] => 10658462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Vertically stacked dual channel nanosheet devices [patent_app_type] => utility [patent_app_number] => 16/584168 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584168 [rel_patent_id] =>[rel_patent_doc_number] =>)