Search

Tong-ho Kim

Examiner (ID: 282, Phone: (571)270-0276 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1305
Issued Applications
1141
Pending Applications
141
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16677741 [patent_doc_number] => 20210066507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/962256 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962256
Semiconductor device and method for manufacturing semiconductor device Jan 14, 2019 Issued
Array ( [id] => 15000515 [patent_doc_number] => 20190319215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => DISPLAY DEVICE INCLUDING A STRESS NEUTRALIZING LAYER [patent_app_type] => utility [patent_app_number] => 16/244325 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244325
Display device including a stress neutralizing layer Jan 9, 2019 Issued
Array ( [id] => 15200717 [patent_doc_number] => 10497865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => RRAM device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/242636 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3442 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242636
RRAM device and method for manufacturing the same Jan 7, 2019 Issued
Array ( [id] => 16021567 [patent_doc_number] => 20200185627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => FOLDABLE DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND FOLDABLE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/337439 [patent_app_country] => US [patent_app_date] => 2018-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337439
Foldable display panel, manufacturing method thereof and foldable display device Dec 24, 2018 Issued
Array ( [id] => 16098515 [patent_doc_number] => 20200203244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MULTI-DIE MODULE WITH SUBSTRATE CAVITY ASSEMBLY [patent_app_type] => utility [patent_app_number] => 16/231559 [patent_app_country] => US [patent_app_date] => 2018-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231559
Multi-die module with substrate cavity assembly Dec 22, 2018 Issued
Array ( [id] => 16645589 [patent_doc_number] => 10923457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Multi-die module with contactless coupler and a coupling loss reduction structure [patent_app_type] => utility [patent_app_number] => 16/231555 [patent_app_country] => US [patent_app_date] => 2018-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6798 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16231555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/231555
Multi-die module with contactless coupler and a coupling loss reduction structure Dec 22, 2018 Issued
Array ( [id] => 16098885 [patent_doc_number] => 20200203429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => THREE-DIMENSIONAL MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/228952 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228952
Three-dimensional memory array Dec 20, 2018 Issued
Array ( [id] => 15369853 [patent_doc_number] => 20200020691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/229207 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229207
Semiconductor devices Dec 20, 2018 Issued
Array ( [id] => 16280189 [patent_doc_number] => 10763230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Integrated circuit backside metallization [patent_app_type] => utility [patent_app_number] => 16/228962 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3319 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228962
Integrated circuit backside metallization Dec 20, 2018 Issued
Array ( [id] => 15889529 [patent_doc_number] => 10651119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor module and method of manufacturing semiconductor module [patent_app_type] => utility [patent_app_number] => 16/228458 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 4456 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228458
Semiconductor module and method of manufacturing semiconductor module Dec 19, 2018 Issued
Array ( [id] => 15703531 [patent_doc_number] => 10607953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => Substrate-less waveguide active circuit module with current mode power combining [patent_app_type] => utility [patent_app_number] => 16/228438 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228438 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228438
Substrate-less waveguide active circuit module with current mode power combining Dec 19, 2018 Issued
Array ( [id] => 15428011 [patent_doc_number] => 10546945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism [patent_app_type] => utility [patent_app_number] => 16/226847 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 13889 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226847
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism Dec 19, 2018 Issued
Array ( [id] => 14753369 [patent_doc_number] => 20190259858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SUB-THERMAL SWITCHING SLOPE VERTICAL FIELD EFFECT TRANSISTOR WITH DUAL-GATE FEEDBACK LOOP MECHANISM [patent_app_type] => utility [patent_app_number] => 16/226876 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226876 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226876
Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism Dec 19, 2018 Issued
Array ( [id] => 15857329 [patent_doc_number] => 10643961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Substrate-less waveguide active circuit module [patent_app_type] => utility [patent_app_number] => 16/228365 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228365 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228365
Substrate-less waveguide active circuit module Dec 19, 2018 Issued
Array ( [id] => 17353307 [patent_doc_number] => 11227954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Two-channel semiconductor component [patent_app_type] => utility [patent_app_number] => 16/958549 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 8043 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 457 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16958549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/958549
Two-channel semiconductor component Dec 18, 2018 Issued
Array ( [id] => 16394689 [patent_doc_number] => 20200335630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/954585 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16954585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/954585
Semiconductor device and method for manufacturing semiconductor device Dec 18, 2018 Issued
Array ( [id] => 17893402 [patent_doc_number] => 11456386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Thin film transistor, manufacturing method thereof, array substrate and electronic device [patent_app_type] => utility [patent_app_number] => 16/468760 [patent_app_country] => US [patent_app_date] => 2018-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 10363 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16468760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/468760
Thin film transistor, manufacturing method thereof, array substrate and electronic device Dec 13, 2018 Issued
Array ( [id] => 14164197 [patent_doc_number] => 20190109201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => MOS-VARACTOR DESIGN TO IMPROVE TUNING EFFICIENCY [patent_app_type] => utility [patent_app_number] => 16/214201 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16214201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/214201
MOS-varactor design to improve tuning efficiency Dec 9, 2018 Issued
Array ( [id] => 16202221 [patent_doc_number] => 10727403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Resistive memory device and method of manufacturing the resistive memory device [patent_app_type] => utility [patent_app_number] => 16/210806 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5779 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16210806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/210806
Resistive memory device and method of manufacturing the resistive memory device Dec 4, 2018 Issued
Array ( [id] => 16293434 [patent_doc_number] => 10770288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Selective capping processes and structures formed thereby [patent_app_type] => utility [patent_app_number] => 16/206192 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 12616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206192
Selective capping processes and structures formed thereby Nov 29, 2018 Issued
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