Search

Tong-ho Kim

Examiner (ID: 282, Phone: (571)270-0276 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1305
Issued Applications
1141
Pending Applications
141
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15200433 [patent_doc_number] => 10497719 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method for selectively increasing silicon fin area for vertical field effect transistors [patent_app_type] => utility [patent_app_number] => 15/880156 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4012 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880156
Method for selectively increasing silicon fin area for vertical field effect transistors Jan 24, 2018 Issued
Array ( [id] => 14221301 [patent_doc_number] => 20190123035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => METHOD OF PERFORMING DIE-BASED HETEROGENEOUS INTEGRATION AND DEVICES INCLUDING INTEGRATED DIES [patent_app_type] => utility [patent_app_number] => 15/880349 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880349
METHOD OF PERFORMING DIE-BASED HETEROGENEOUS INTEGRATION AND DEVICES INCLUDING INTEGRATED DIES Jan 24, 2018 Abandoned
Array ( [id] => 14381825 [patent_doc_number] => 20190164825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => PHYSICAL VAPOR DEPOSITION PROCESS FOR SEMICONDUCTOR INTERCONNECTION STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/880324 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880324 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880324
Physical vapor deposition process for semiconductor interconnection structures Jan 24, 2018 Issued
Array ( [id] => 14381677 [patent_doc_number] => 20190164751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => Selective Capping Processes and Structures Formed Thereby [patent_app_type] => utility [patent_app_number] => 15/880389 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880389
Selective capping processes and structures formed thereby Jan 24, 2018 Issued
Array ( [id] => 14151625 [patent_doc_number] => 10256202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits [patent_app_type] => utility [patent_app_number] => 15/880139 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4331 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880139
Durable bond pad structure for electrical connection to extreme environment microelectronic integrated circuits Jan 24, 2018 Issued
Array ( [id] => 15885381 [patent_doc_number] => 10649027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device including test circuit [patent_app_type] => utility [patent_app_number] => 15/879498 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2611 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879498
Semiconductor device including test circuit Jan 24, 2018 Issued
Array ( [id] => 15885381 [patent_doc_number] => 10649027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device including test circuit [patent_app_type] => utility [patent_app_number] => 15/879498 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2611 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879498
Semiconductor device including test circuit Jan 24, 2018 Issued
Array ( [id] => 15885381 [patent_doc_number] => 10649027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Semiconductor device including test circuit [patent_app_type] => utility [patent_app_number] => 15/879498 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2611 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879498
Semiconductor device including test circuit Jan 24, 2018 Issued
Array ( [id] => 14125631 [patent_doc_number] => 10249680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Thermal management of selector [patent_app_type] => utility [patent_app_number] => 15/874977 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874977
Thermal management of selector Jan 18, 2018 Issued
Array ( [id] => 12739309 [patent_doc_number] => 20180138270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Nanowire Semiconductor Device Structure and Method of Manufacturing [patent_app_type] => utility [patent_app_number] => 15/871725 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871725
Nanowire semiconductor device structure and method of manufacturing Jan 14, 2018 Issued
Array ( [id] => 16495661 [patent_doc_number] => 10861709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Method of evaluating impurity gettering capability of epitaxial silicon wafer and epitaxial silicon wafer [patent_app_type] => utility [patent_app_number] => 16/488758 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7397 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16488758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/488758
Method of evaluating impurity gettering capability of epitaxial silicon wafer and epitaxial silicon wafer Jan 11, 2018 Issued
Array ( [id] => 17544265 [patent_doc_number] => 11309400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Stacked thin film transistors with nanowires [patent_app_type] => utility [patent_app_number] => 16/650153 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650153
Stacked thin film transistors with nanowires Jan 11, 2018 Issued
Array ( [id] => 12801265 [patent_doc_number] => 20180158924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SLOPED FINFET WITH METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 15/868274 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868274
Sloped finFET with methods of forming same Jan 10, 2018 Issued
Array ( [id] => 15170427 [patent_doc_number] => 10490720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Micro light-emitting device and display apparatus [patent_app_type] => utility [patent_app_number] => 15/867722 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867722
Micro light-emitting device and display apparatus Jan 10, 2018 Issued
Array ( [id] => 15791941 [patent_doc_number] => 10629703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Sloped finFET with methods of forming same [patent_app_type] => utility [patent_app_number] => 15/868224 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868224 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868224
Sloped finFET with methods of forming same Jan 10, 2018 Issued
Array ( [id] => 15170077 [patent_doc_number] => 10490544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Memory circuit layout [patent_app_type] => utility [patent_app_number] => 15/863090 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863090
Memory circuit layout Jan 4, 2018 Issued
Array ( [id] => 16286243 [patent_doc_number] => 20200279845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => TRANSISTOR STRUCTURES HAVING MULTIPLE THRESHOLD VOLTAGE CHANNEL MATERIALS [patent_app_type] => utility [patent_app_number] => 16/650823 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650823 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650823
Transistor structures having multiple threshold voltage channel materials Jan 4, 2018 Issued
Array ( [id] => 15030995 [patent_doc_number] => 20190326502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SUPERCONDUCTIVE JUNCTION, SUPERCONDUCTING APPARATUS, METHOD OF MANUFACTURING SUPERCONDUCTING JUNCTION AND CONTROL METHOD OF SUPERCONDUCTING JUNCTION [patent_app_type] => utility [patent_app_number] => 16/474789 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16474789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/474789
Superconductive junction, superconducting apparatus, method of manufacturing superconducting junction and control method of superconducting junction Dec 27, 2017 Issued
Array ( [id] => 17181461 [patent_doc_number] => 11158711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Air gap for thin film transistors [patent_app_type] => utility [patent_app_number] => 16/645405 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9919 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16645405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/645405
Air gap for thin film transistors Dec 26, 2017 Issued
Array ( [id] => 12668887 [patent_doc_number] => 20180114795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Methods Of Processing Silicon Nitride-Comprising Materials [patent_app_type] => utility [patent_app_number] => 15/851532 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851532 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851532
Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials Dec 20, 2017 Issued
Menu