
Tong-ho Kim
Examiner (ID: 9651, Phone: (571)270-0276 , Office: P/2811 )
| Most Active Art Unit | 2811 |
| Art Unit(s) | 2811 |
| Total Applications | 1259 |
| Issued Applications | 1112 |
| Pending Applications | 128 |
| Abandoned Applications | 51 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18714790
[patent_doc_number] => 20230337435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => 3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC CHANNEL REGIONS
[patent_app_type] => utility
[patent_app_number] => 18/336678
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6211
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336678
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/336678 | 3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC CHANNEL REGIONS | Jun 15, 2023 | Pending |
Array
(
[id] => 19646685
[patent_doc_number] => 20240421205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/336377
[patent_app_country] => US
[patent_app_date] => 2023-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8047
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336377
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/336377 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF | Jun 15, 2023 | Pending |
Array
(
[id] => 18696411
[patent_doc_number] => 20230326850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-12
[patent_title] => Semiconductor Device and Method of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/334843
[patent_app_country] => US
[patent_app_date] => 2023-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9185
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334843
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/334843 | Semiconductor device and method of manufacture | Jun 13, 2023 | Issued |
Array
(
[id] => 19229660
[patent_doc_number] => 12009304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Integrated circuit and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/334136
[patent_app_country] => US
[patent_app_date] => 2023-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 126
[patent_figures_cnt] => 135
[patent_no_of_words] => 15207
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334136
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/334136 | Integrated circuit and method for forming the same | Jun 12, 2023 | Issued |
Array
(
[id] => 19646440
[patent_doc_number] => 20240420960
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => INVERTED GATE CUT REGION
[patent_app_type] => utility
[patent_app_number] => 18/333832
[patent_app_country] => US
[patent_app_date] => 2023-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16196
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333832
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/333832 | INVERTED GATE CUT REGION | Jun 12, 2023 | Pending |
Array
(
[id] => 19634770
[patent_doc_number] => 20240413219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => FIELD-EFFECT TRANSISTORS (FETS) EMPLOYING THERMAL EXPANSION OF WORK FUNCTION METAL LAYERS FOR STRAIN EFFECT AND RELATED FABRICATION METHODS
[patent_app_type] => utility
[patent_app_number] => 18/333004
[patent_app_country] => US
[patent_app_date] => 2023-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10649
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333004
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/333004 | FIELD-EFFECT TRANSISTORS (FETS) EMPLOYING THERMAL EXPANSION OF WORK FUNCTION METAL LAYERS FOR STRAIN EFFECT AND RELATED FABRICATION METHODS | Jun 11, 2023 | Pending |
Array
(
[id] => 20540548
[patent_doc_number] => 12557637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-17
[patent_title] => Stacked transistors with metal vias
[patent_app_type] => utility
[patent_app_number] => 18/332947
[patent_app_country] => US
[patent_app_date] => 2023-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 52
[patent_no_of_words] => 4035
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332947
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/332947 | Stacked transistors with metal vias | Jun 11, 2023 | Issued |
Array
(
[id] => 18679864
[patent_doc_number] => 20230317522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => SEMICONDUCTOR DEVICE WITH FIN STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 18/331326
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7350
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331326
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/331326 | Semiconductor device with fin structures | Jun 7, 2023 | Issued |
Array
(
[id] => 18906191
[patent_doc_number] => 20240021676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/331463
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12673
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/331463 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME | Jun 7, 2023 | Pending |
Array
(
[id] => 19634752
[patent_doc_number] => 20240413201
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => SELF-ALIGNED BACKSIDE CONTACT WITH PROTRUDING SOURCE/DRAIN
[patent_app_type] => utility
[patent_app_number] => 18/329668
[patent_app_country] => US
[patent_app_date] => 2023-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329668
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/329668 | Self-aligned backside contact with protruding source/drain | Jun 5, 2023 | Issued |
Array
(
[id] => 19619269
[patent_doc_number] => 20240404949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => METAL INTERCONNECT LAYERS FOR FET ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/206060
[patent_app_country] => US
[patent_app_date] => 2023-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206060
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206060 | METAL INTERCONNECT LAYERS FOR FET ARCHITECTURES | Jun 4, 2023 | Pending |
Array
(
[id] => 19619270
[patent_doc_number] => 20240404950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING BACKSIDE SIGNAL WIRING AND FRONTSIDE POWER SUPPLY
[patent_app_type] => utility
[patent_app_number] => 18/327444
[patent_app_country] => US
[patent_app_date] => 2023-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10186
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327444
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/327444 | SEMICONDUCTOR DEVICE INCLUDING BACKSIDE SIGNAL WIRING AND FRONTSIDE POWER SUPPLY | May 31, 2023 | Pending |
Array
(
[id] => 18817272
[patent_doc_number] => 20230391612
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => SELF-ASSEMBLED HIERARCHICAL POROUS Pd@PdPt YOLK-SHELL NANOARCHITICTONICS AND HOLLOW PdPt NANOCAGES HYDROGEN SENSORS
[patent_app_type] => utility
[patent_app_number] => 18/204513
[patent_app_country] => US
[patent_app_date] => 2023-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7732
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204513
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/204513 | Self-assembled hierarchical porous Pd@PdPt yolk-shell nanoarchitictonics and hollow PdPt nanocages hydrogen sensors | May 31, 2023 | Issued |
Array
(
[id] => 19123651
[patent_doc_number] => 11967646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-23
[patent_title] => Thin film transistor structure, display panel and display device
[patent_app_type] => utility
[patent_app_number] => 18/327217
[patent_app_country] => US
[patent_app_date] => 2023-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 7227
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327217
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/327217 | Thin film transistor structure, display panel and display device | May 31, 2023 | Issued |
Array
(
[id] => 19371693
[patent_doc_number] => 12063798
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Semiconductor device and method for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/203736
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 40
[patent_no_of_words] => 39246
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203736
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/203736 | Semiconductor device and method for manufacturing semiconductor device | May 30, 2023 | Issued |
Array
(
[id] => 18653337
[patent_doc_number] => 20230299177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => Electroless Plating Method for Metal Gate Fill
[patent_app_type] => utility
[patent_app_number] => 18/324442
[patent_app_country] => US
[patent_app_date] => 2023-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324442
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/324442 | Electroless plating method for metal gate fill | May 25, 2023 | Issued |
Array
(
[id] => 18653326
[patent_doc_number] => 20230299166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => NANOWIRE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/201769
[patent_app_country] => US
[patent_app_date] => 2023-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3094
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201769
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201769 | Nanowire transistor and method for fabricating the same | May 24, 2023 | Issued |
Array
(
[id] => 19131077
[patent_doc_number] => 20240136430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/201878
[patent_app_country] => US
[patent_app_date] => 2023-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14293
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201878
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201878 | SEMICONDUCTOR DEVICE | May 24, 2023 | Pending |
Array
(
[id] => 19131077
[patent_doc_number] => 20240136430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-25
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/201878
[patent_app_country] => US
[patent_app_date] => 2023-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14293
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201878
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201878 | SEMICONDUCTOR DEVICE | May 23, 2023 | Pending |
Array
(
[id] => 18655200
[patent_doc_number] => 20230301051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => INTEGRATED CIRCUIT WITH EMBEDDED HIGH-DENSITY AND HIGH-CURRENT SRAM MACROS
[patent_app_type] => utility
[patent_app_number] => 18/320494
[patent_app_country] => US
[patent_app_date] => 2023-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15778
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320494
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/320494 | Integrated circuit with embedded high-density and high-current SRAM macros | May 18, 2023 | Issued |