Search

Toniae M. Thomas

Examiner (ID: 17248)

Most Active Art Unit
2822
Art Unit(s)
1104, 1763, 2822, 2813
Total Applications
1101
Issued Applications
969
Pending Applications
9
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6176261 [patent_doc_number] => 20110177639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL' [patent_app_type] => utility [patent_app_number] => 12/767667 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5378 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20110177639.pdf [firstpage_image] =>[orig_patent_app_number] => 12767667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767667
Method for manufacturing a thin film transistor array panel Apr 25, 2010 Issued
Array ( [id] => 6570135 [patent_doc_number] => 20100273316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'METHOD FOR FABRICATING SILICON AND/OR GERMANIUM NANOWIRES' [patent_app_type] => utility [patent_app_number] => 12/767707 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273316.pdf [firstpage_image] =>[orig_patent_app_number] => 12767707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767707
Method for fabricating silicon and/or germanium nanowires Apr 25, 2010 Issued
Array ( [id] => 8398277 [patent_doc_number] => 08268656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Optical device wafer processing method' [patent_app_type] => utility [patent_app_number] => 12/759338 [patent_app_country] => US [patent_app_date] => 2010-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5907 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12759338 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759338
Optical device wafer processing method Apr 12, 2010 Issued
Array ( [id] => 4608805 [patent_doc_number] => 07993990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Multiple crystallographic orientation semiconductor structures' [patent_app_type] => utility [patent_app_number] => 12/757567 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/993/07993990.pdf [firstpage_image] =>[orig_patent_app_number] => 12757567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757567
Multiple crystallographic orientation semiconductor structures Apr 8, 2010 Issued
Array ( [id] => 7732576 [patent_doc_number] => 20120015472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'METHOD OF PRODUCING SOLAR CELL MODULE' [patent_app_type] => utility [patent_app_number] => 13/138747 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 58936 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20120015472.pdf [firstpage_image] =>[orig_patent_app_number] => 13138747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/138747
METHOD OF PRODUCING SOLAR CELL MODULE Mar 23, 2010 Abandoned
Array ( [id] => 6345231 [patent_doc_number] => 20100248420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'METHOD FOR FORMING AN ABSORBER LAYER OF A THIN FILM SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 12/729907 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3887 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20100248420.pdf [firstpage_image] =>[orig_patent_app_number] => 12729907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729907
Method for forming an absorber layer of a thin film solar cell Mar 22, 2010 Issued
Array ( [id] => 6295113 [patent_doc_number] => 20100240192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'ALIGNMENT MARK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MASK SET' [patent_app_type] => utility [patent_app_number] => 12/726697 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20100240192.pdf [firstpage_image] =>[orig_patent_app_number] => 12726697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726697
Alignment mark, method of manufacturing semiconductor device, and mask set Mar 17, 2010 Issued
Array ( [id] => 6433056 [patent_doc_number] => 20100187654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Semiconductor device having capacitor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/659724 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6830 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20100187654.pdf [firstpage_image] =>[orig_patent_app_number] => 12659724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659724
Semiconductor device having capacitor Mar 17, 2010 Issued
Array ( [id] => 6295106 [patent_doc_number] => 20100240189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'Methods of Fabricating Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 12/725647 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20100240189.pdf [firstpage_image] =>[orig_patent_app_number] => 12725647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725647
Methods of fabricating semiconductor devices Mar 16, 2010 Issued
Array ( [id] => 6400521 [patent_doc_number] => 20100148273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS' [patent_app_type] => utility [patent_app_number] => 12/712371 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8874 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148273.pdf [firstpage_image] =>[orig_patent_app_number] => 12712371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712371
CMOS transistors with differential oxygen content high-K dielectrics Feb 24, 2010 Issued
Array ( [id] => 6528836 [patent_doc_number] => 20100203703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Deep Trench Isolation Structures and Methods of Formation Thereof' [patent_app_type] => utility [patent_app_number] => 12/702368 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20100203703.pdf [firstpage_image] =>[orig_patent_app_number] => 12702368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702368
Deep trench isolation structures and methods of formation thereof Feb 8, 2010 Issued
Array ( [id] => 6240084 [patent_doc_number] => 20100133558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'FLIP CHIP TYPE LED LIGHTING DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/700853 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20100133558.pdf [firstpage_image] =>[orig_patent_app_number] => 12700853 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700853
Flip chip type LED lighting device manufacturing method Feb 4, 2010 Issued
Array ( [id] => 7732577 [patent_doc_number] => 20120015473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD, PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM, AND METHOD FOR USING PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/146624 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 22290 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20120015473.pdf [firstpage_image] =>[orig_patent_app_number] => 13146624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/146624
PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING METHOD, PHOTOELECTRIC CONVERSION DEVICE, PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM, AND METHOD FOR USING PHOTOELECTRIC CONVERSION DEVICE MANUFACTURING SYSTEM Jan 28, 2010 Abandoned
Array ( [id] => 7480910 [patent_doc_number] => 20110233719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE \"SEMICONDUCTOR ON INSULATOR\" TYPE' [patent_app_type] => utility [patent_app_number] => 13/133118 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3885 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233719.pdf [firstpage_image] =>[orig_patent_app_number] => 13133118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/133118
TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE "SEMICONDUCTOR ON INSULATOR" TYPE Jan 13, 2010 Abandoned
Array ( [id] => 7669655 [patent_doc_number] => 20110318924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'METHOD FOR DEPOSITION OF AT LEAST ONE ELECTRICALLY CONDUCTING FILM ON A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/143940 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3394 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13143940 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/143940
Method for deposition of at least one electrically conducting film on a substrate Jan 10, 2010 Issued
Array ( [id] => 7669670 [patent_doc_number] => 20110318939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'HIGH ORDER SILANE COMPOSITION AND METHOD OF MANUFACTURING A FILM-COATED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/143854 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 10630 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13143854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/143854
High order silane composition and method of manufacturing a film-coated substrate Jan 6, 2010 Issued
Array ( [id] => 8560093 [patent_doc_number] => 08334156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same' [patent_app_type] => utility [patent_app_number] => 12/648787 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648787 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648787
Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same Dec 28, 2009 Issued
Array ( [id] => 6608873 [patent_doc_number] => 20100099206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 12/645448 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7834 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20100099206.pdf [firstpage_image] =>[orig_patent_app_number] => 12645448 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645448
Manufacturing method of thin film transistor array substrate and liquid crystal display panel Dec 21, 2009 Issued
Array ( [id] => 6293022 [patent_doc_number] => 20100159638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Method of fabricating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/655047 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7782 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159638.pdf [firstpage_image] =>[orig_patent_app_number] => 12655047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655047
Method of fabricating nonvolatile memory device Dec 20, 2009 Issued
Array ( [id] => 6419415 [patent_doc_number] => 20100167530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/643908 [patent_app_country] => US [patent_app_date] => 2009-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20100167530.pdf [firstpage_image] =>[orig_patent_app_number] => 12643908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/643908
METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE Dec 20, 2009 Abandoned
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