Search

Toniae M. Thomas

Examiner (ID: 17248)

Most Active Art Unit
2822
Art Unit(s)
1104, 1763, 2822, 2813
Total Applications
1101
Issued Applications
969
Pending Applications
9
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6633350 [patent_doc_number] => 20100173444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'MANUFACTURING METHOD OF A PHOTOELECTRIC CONVERSION DEVICE' [patent_app_type] => utility [patent_app_number] => 12/622747 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8233 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20100173444.pdf [firstpage_image] =>[orig_patent_app_number] => 12622747 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622747
Manufacturing method of a photoelectric conversion device Nov 19, 2009 Issued
Array ( [id] => 8305784 [patent_doc_number] => 08227318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation' [patent_app_type] => utility [patent_app_number] => 12/622028 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12622028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622028
Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation Nov 18, 2009 Issued
Array ( [id] => 8807688 [patent_doc_number] => 08445340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Sacrificial offset protection film for a FinFET device' [patent_app_type] => utility [patent_app_number] => 12/622038 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12622038 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/622038
Sacrificial offset protection film for a FinFET device Nov 18, 2009 Issued
Array ( [id] => 6001871 [patent_doc_number] => 20110117710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'METHOD OF FABRICATING EFUSE, RESISTOR AND TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/621518 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2888 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20110117710.pdf [firstpage_image] =>[orig_patent_app_number] => 12621518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621518
Method of fabricating efuse, resistor and transistor Nov 18, 2009 Issued
Array ( [id] => 6001894 [patent_doc_number] => 20110117733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'Methods Of Utilizing Block Copolymers To Form Patterns' [patent_app_type] => utility [patent_app_number] => 12/621768 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15907 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20110117733.pdf [firstpage_image] =>[orig_patent_app_number] => 12621768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621768
Methods of utilizing block copolymers to form patterns Nov 18, 2009 Issued
Array ( [id] => 8571580 [patent_doc_number] => 08338224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Resistance-type random access memory device having three-dimensional bit line and word line patterning' [patent_app_type] => utility [patent_app_number] => 12/621007 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 54 [patent_no_of_words] => 12046 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12621007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621007
Resistance-type random access memory device having three-dimensional bit line and word line patterning Nov 17, 2009 Issued
Array ( [id] => 7711991 [patent_doc_number] => 08093072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Substrate processing apparatus and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/618248 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7147 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093072.pdf [firstpage_image] =>[orig_patent_app_number] => 12618248 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618248
Substrate processing apparatus and method of manufacturing semiconductor device Nov 12, 2009 Issued
Array ( [id] => 9233319 [patent_doc_number] => 08598627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'P-type field-effect transistor and method of production' [patent_app_type] => utility [patent_app_number] => 13/127318 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13127318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/127318
P-type field-effect transistor and method of production Nov 11, 2009 Issued
Array ( [id] => 7685913 [patent_doc_number] => 20100120228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'SEMICONDUTOR MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/615277 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9249 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20100120228.pdf [firstpage_image] =>[orig_patent_app_number] => 12615277 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615277
Semiconductor manufacturing method Nov 9, 2009 Issued
Array ( [id] => 7685952 [patent_doc_number] => 20100120189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD FOR MANUFACTURING IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 12/615088 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20100120189.pdf [firstpage_image] =>[orig_patent_app_number] => 12615088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/615088
Method for manufacturing image sensor Nov 8, 2009 Issued
Array ( [id] => 6096616 [patent_doc_number] => 20110003459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'METHOD FOR FABRICATING BURIED GATE USING PRE LANDING PLUGS' [patent_app_type] => utility [patent_app_number] => 12/613708 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7653 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20110003459.pdf [firstpage_image] =>[orig_patent_app_number] => 12613708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613708
Method for fabricating buried gate using pre landing plugs Nov 5, 2009 Issued
Array ( [id] => 6398784 [patent_doc_number] => 20100178761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'Stacked Integrated Chips and Methods of Fabrication Thereof' [patent_app_type] => utility [patent_app_number] => 12/613408 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20100178761.pdf [firstpage_image] =>[orig_patent_app_number] => 12613408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613408
Stacked integrated chips and methods of fabrication thereof Nov 4, 2009 Issued
Array ( [id] => 6317824 [patent_doc_number] => 20100112743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING VIBRATOR WHICH IS PROVIDED WITH SIDE INSULATING FILM AND INSULATING SEPARATION REGION FORMED BY THERMAL OXIDATION' [patent_app_type] => utility [patent_app_number] => 12/612008 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20100112743.pdf [firstpage_image] =>[orig_patent_app_number] => 12612008 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612008
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING VIBRATOR WHICH IS PROVIDED WITH SIDE INSULATING FILM AND INSULATING SEPARATION REGION FORMED BY THERMAL OXIDATION Nov 3, 2009 Abandoned
Array ( [id] => 5944207 [patent_doc_number] => 20110104827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Template-Registered DiBlock Copolymer Mask for MRAM Device Formation' [patent_app_type] => utility [patent_app_number] => 12/612258 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2574 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20110104827.pdf [firstpage_image] =>[orig_patent_app_number] => 12612258 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612258
Template-registered diblock copolymer mask for MRAM device formation Nov 3, 2009 Issued
Array ( [id] => 6324099 [patent_doc_number] => 20100197068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Hybrid Transparent Conductive Electrode' [patent_app_type] => utility [patent_app_number] => 12/610247 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16771 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20100197068.pdf [firstpage_image] =>[orig_patent_app_number] => 12610247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610247
Hybrid Transparent Conductive Electrode Oct 29, 2009 Abandoned
Array ( [id] => 7701630 [patent_doc_number] => 08087380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Evaporative system for solar cell fabrication' [patent_app_type] => utility [patent_app_number] => 12/610187 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3209 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/087/08087380.pdf [firstpage_image] =>[orig_patent_app_number] => 12610187 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610187
Evaporative system for solar cell fabrication Oct 29, 2009 Issued
Array ( [id] => 9183808 [patent_doc_number] => 08623740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Method of detaching semi-conductor layers at low temperature' [patent_app_type] => utility [patent_app_number] => 13/126655 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13126655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/126655
Method of detaching semi-conductor layers at low temperature Oct 28, 2009 Issued
Array ( [id] => 6247679 [patent_doc_number] => 20100136775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/607567 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7081 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20100136775.pdf [firstpage_image] =>[orig_patent_app_number] => 12607567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/607567
METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE Oct 27, 2009 Abandoned
Array ( [id] => 4517766 [patent_doc_number] => 07932546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Image sensor having microlenses and high photosensitivity' [patent_app_type] => utility [patent_app_number] => 12/606595 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5066 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932546.pdf [firstpage_image] =>[orig_patent_app_number] => 12606595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606595
Image sensor having microlenses and high photosensitivity Oct 26, 2009 Issued
Array ( [id] => 5985754 [patent_doc_number] => 20110097859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'METHOD OF FABRICATING CMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 12/605377 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20110097859.pdf [firstpage_image] =>[orig_patent_app_number] => 12605377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605377
Method of fabricating CMOS transistor Oct 25, 2009 Issued
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