Toniae M. Thomas

Array ( [id] => 4727444 [patent_doc_number] => 20080206988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Formation of fully silicided gate with oxide barrier on the source/drain silicide regions' [patent_app_type] => utility [patent_app_number] => 11/711297 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5626 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206988.pdf [firstpage_image] =>[orig_patent_app_number] => 11711297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4725482 [patent_doc_number] => 20080205023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 11/679407 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1608 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205023.pdf [firstpage_image] =>[orig_patent_app_number] => 11679407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4727398 [patent_doc_number] => 20080206942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/678627 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3007 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206942.pdf [firstpage_image] =>[orig_patent_app_number] => 11678627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 196562 [patent_doc_number] => 07638377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/710658 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 89 [patent_no_of_words] => 28922 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/638/07638377.pdf [firstpage_image] =>[orig_patent_app_number] => 11710658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4870690 [patent_doc_number] => 20080197424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'SEMICONDUCTOR STRUCTURE INCLUDING GATE ELECTRODE HAVING LATERALLY VARIABLE WORK FUNCTION' [patent_app_type] => utility [patent_app_number] => 11/677207 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6901 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20080197424.pdf [firstpage_image] =>[orig_patent_app_number] => 11677207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 220966 [patent_doc_number] => 07608512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Integrated circuit structure with improved LDMOS design' [patent_app_type] => utility [patent_app_number] => 11/675759 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3335 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608512.pdf [firstpage_image] =>[orig_patent_app_number] => 11675759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4813435 [patent_doc_number] => 20080194066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates' [patent_app_type] => utility [patent_app_number] => 11/706177 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5392 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20080194066.pdf [firstpage_image] =>[orig_patent_app_number] => 11706177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5233955 [patent_doc_number] => 20070126110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'CIRCUIT FILM WITH BUMP, FILM PACKAGE USING THE SAME, AND RELATED FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 11/670847 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20070126110.pdf [firstpage_image] =>[orig_patent_app_number] => 11670847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4843230 [patent_doc_number] => 20080179638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS' [patent_app_type] => utility [patent_app_number] => 11/669287 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 8118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179638.pdf [firstpage_image] =>[orig_patent_app_number] => 11669287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4845967 [patent_doc_number] => 20080182375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'SPLIT GATE MEMORY CELL METHOD' [patent_app_type] => utility [patent_app_number] => 11/669307 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20080182375.pdf [firstpage_image] =>[orig_patent_app_number] => 11669307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 24911 [patent_doc_number] => 07795682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Semiconductor device and method manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/700147 [patent_app_country] => US [patent_app_date] => 2007-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 38 [patent_no_of_words] => 9752 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795682.pdf [firstpage_image] =>[orig_patent_app_number] => 11700147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500031 [patent_doc_number] => 07919372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Method for forming oxide on ONO structure' [patent_app_type] => utility [patent_app_number] => 11/625177 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5083 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919372.pdf [firstpage_image] =>[orig_patent_app_number] => 11625177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5095743 [patent_doc_number] => 20070117352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Method for dicing semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/655008 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3050 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117352.pdf [firstpage_image] =>[orig_patent_app_number] => 11655008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5095691 [patent_doc_number] => 20070117300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'METHOD OF FORMING SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR SUBSTRATE AND SOI SEMICONDUCTOR SUBSTRATE FORMED THEREBY' [patent_app_type] => utility [patent_app_number] => 11/623384 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3624 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117300.pdf [firstpage_image] =>[orig_patent_app_number] => 11623384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4394 [patent_doc_number] => 07811874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/281902 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4414 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/811/07811874.pdf [firstpage_image] =>[orig_patent_app_number] => 12281902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4807842 [patent_doc_number] => 20080171420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'STRUCTURE AND METHOD TO FORM IMPROVED ISOLATION IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/622057 [patent_app_country] => US [patent_app_date] => 2007-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20080171420.pdf [firstpage_image] =>[orig_patent_app_number] => 11622057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4577419 [patent_doc_number] => 07855442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Silicon based package' [patent_app_type] => utility [patent_app_number] => 11/650883 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 49 [patent_no_of_words] => 11306 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855442.pdf [firstpage_image] =>[orig_patent_app_number] => 11650883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4971494 [patent_doc_number] => 20070111496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Semiconductor device having dual stacked MIM capacitor and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/649830 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5959 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111496.pdf [firstpage_image] =>[orig_patent_app_number] => 11649830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307344 [patent_doc_number] => 07531410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor flash memory device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/648057 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4285 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531410.pdf [firstpage_image] =>[orig_patent_app_number] => 11648057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4988745 [patent_doc_number] => 20070155084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'CMOS image sensor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/646797 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155084.pdf [firstpage_image] =>[orig_patent_app_number] => 11646797 [rel_patent_id] =>[rel_patent_doc_number] =>)