Search

Toniae M. Thomas

Examiner (ID: 17248)

Most Active Art Unit
2822
Art Unit(s)
1104, 1763, 2822, 2813
Total Applications
1101
Issued Applications
969
Pending Applications
9
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4455982 [patent_doc_number] => 07892985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing' [patent_app_type] => utility [patent_app_number] => 11/280113 [patent_app_country] => US [patent_app_date] => 2005-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5995 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/892/07892985.pdf [firstpage_image] =>[orig_patent_app_number] => 11280113 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/280113
Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing Nov 14, 2005 Issued
Array ( [id] => 918372 [patent_doc_number] => 07323780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Electrical interconnection structure formation' [patent_app_type] => utility [patent_app_number] => 11/164107 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3461 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/323/07323780.pdf [firstpage_image] =>[orig_patent_app_number] => 11164107 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164107
Electrical interconnection structure formation Nov 9, 2005 Issued
Array ( [id] => 5828315 [patent_doc_number] => 20060063339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Multi-bit stacked-type non-volatile memory and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 11/269671 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2963 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063339.pdf [firstpage_image] =>[orig_patent_app_number] => 11269671 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269671
Multi-bit stacked-type non-volatile memory Nov 8, 2005 Issued
Array ( [id] => 5727051 [patent_doc_number] => 20060057811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Selective post-doping of gate structures by means of selective oxide growth' [patent_app_type] => utility [patent_app_number] => 11/268100 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8915 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20060057811.pdf [firstpage_image] =>[orig_patent_app_number] => 11268100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268100
Selective post-doping of gate structures by means of selective oxide growth Nov 6, 2005 Issued
Array ( [id] => 318644 [patent_doc_number] => 07521354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Low k interlevel dielectric layer fabrication methods' [patent_app_type] => utility [patent_app_number] => 11/266914 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3713 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521354.pdf [firstpage_image] =>[orig_patent_app_number] => 11266914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266914
Low k interlevel dielectric layer fabrication methods Nov 3, 2005 Issued
Array ( [id] => 408747 [patent_doc_number] => 07285813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Metal-insulator-metal capacitor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/265574 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6419 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285813.pdf [firstpage_image] =>[orig_patent_app_number] => 11265574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265574
Metal-insulator-metal capacitor and method for manufacturing the same Nov 1, 2005 Issued
Array ( [id] => 397558 [patent_doc_number] => 07294527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method of forming a memory cell' [patent_app_type] => utility [patent_app_number] => 11/258921 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6694 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294527.pdf [firstpage_image] =>[orig_patent_app_number] => 11258921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258921
Method of forming a memory cell Oct 26, 2005 Issued
Array ( [id] => 581564 [patent_doc_number] => 07456467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure' [patent_app_type] => utility [patent_app_number] => 11/258675 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456467.pdf [firstpage_image] =>[orig_patent_app_number] => 11258675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258675
Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure Oct 24, 2005 Issued
Array ( [id] => 4533642 [patent_doc_number] => 07888217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Method for fabricating a gate dielectric of a field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/255857 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4354 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888217.pdf [firstpage_image] =>[orig_patent_app_number] => 11255857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255857
Method for fabricating a gate dielectric of a field effect transistor Oct 19, 2005 Issued
Array ( [id] => 4457681 [patent_doc_number] => 07893521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Electric fence energiser' [patent_app_type] => utility [patent_app_number] => 11/242724 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893521.pdf [firstpage_image] =>[orig_patent_app_number] => 11242724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242724
Electric fence energiser Oct 2, 2005 Issued
Array ( [id] => 5767968 [patent_doc_number] => 20060019426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Method for manufacturing CMOS image sensor having microlens therein with high photosensitivity' [patent_app_type] => utility [patent_app_number] => 11/242817 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4988 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019426.pdf [firstpage_image] =>[orig_patent_app_number] => 11242817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242817
Method for manufacturing CMOS image sensor having microlens therein with high photosensitivity Oct 2, 2005 Issued
Array ( [id] => 53778 [patent_doc_number] => 07767527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method for producing a vertical transistor component' [patent_app_type] => utility [patent_app_number] => 11/241867 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 8543 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767527.pdf [firstpage_image] =>[orig_patent_app_number] => 11241867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241867
Method for producing a vertical transistor component Sep 29, 2005 Issued
Array ( [id] => 132656 [patent_doc_number] => 07696079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Methods for patterning films, fabricating organic electroluminescence display and fabricating thin film transistor array substrate' [patent_app_type] => utility [patent_app_number] => 11/162867 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 2976 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696079.pdf [firstpage_image] =>[orig_patent_app_number] => 11162867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162867
Methods for patterning films, fabricating organic electroluminescence display and fabricating thin film transistor array substrate Sep 26, 2005 Issued
Array ( [id] => 568296 [patent_doc_number] => 07462545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Semicondutor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/162727 [patent_app_country] => US [patent_app_date] => 2005-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6685 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462545.pdf [firstpage_image] =>[orig_patent_app_number] => 11162727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162727
Semicondutor device and manufacturing method thereof Sep 20, 2005 Issued
Array ( [id] => 326974 [patent_doc_number] => 07514748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/226978 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3831 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514748.pdf [firstpage_image] =>[orig_patent_app_number] => 11226978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226978
Semiconductor device Sep 14, 2005 Issued
Array ( [id] => 71470 [patent_doc_number] => 07754524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Methods, devices and compositions for depositing and orienting nanostructures' [patent_app_type] => utility [patent_app_number] => 11/226027 [patent_app_country] => US [patent_app_date] => 2005-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7801 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/754/07754524.pdf [firstpage_image] =>[orig_patent_app_number] => 11226027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226027
Methods, devices and compositions for depositing and orienting nanostructures Sep 13, 2005 Issued
Array ( [id] => 5667141 [patent_doc_number] => 20060172491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'NON-VOLATILE MEMORY STRUCTURE AND METHOD OF FABRICATING NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/162497 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2218 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20060172491.pdf [firstpage_image] =>[orig_patent_app_number] => 11162497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162497
Non-volatile memory structure and method of fabricating non-volatile memory Sep 12, 2005 Issued
Array ( [id] => 5608637 [patent_doc_number] => 20060270153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/212627 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7362 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20060270153.pdf [firstpage_image] =>[orig_patent_app_number] => 11212627 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212627
Method for fabricating semiconductor device Aug 28, 2005 Issued
Array ( [id] => 5432213 [patent_doc_number] => 20090166799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUCH A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/574338 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166799.pdf [firstpage_image] =>[orig_patent_app_number] => 11574338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/574338
Method of manufacturing a semiconductor device and such a semiconductor device Aug 9, 2005 Issued
Array ( [id] => 5051483 [patent_doc_number] => 20070032028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'STRUCTURE AND METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/161447 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4412 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20070032028.pdf [firstpage_image] =>[orig_patent_app_number] => 11161447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161447
Structure for reducing overlap capacitance in field effect transistors Aug 2, 2005 Issued
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