Search

Toniae M. Thomas

Examiner (ID: 17248)

Most Active Art Unit
2822
Art Unit(s)
1104, 1763, 2822, 2813
Total Applications
1101
Issued Applications
969
Pending Applications
9
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 314759 [patent_doc_number] => 07524729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device having a trench' [patent_app_type] => utility [patent_app_number] => 11/189833 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 9462 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524729.pdf [firstpage_image] =>[orig_patent_app_number] => 11189833 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/189833
Method of manufacturing a semiconductor integrated circuit device having a trench Jul 26, 2005 Issued
Array ( [id] => 456431 [patent_doc_number] => 07244644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Undercut and residual spacer prevention for dual stressed layers' [patent_app_type] => utility [patent_app_number] => 11/161067 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/244/07244644.pdf [firstpage_image] =>[orig_patent_app_number] => 11161067 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161067
Undercut and residual spacer prevention for dual stressed layers Jul 20, 2005 Issued
Array ( [id] => 7248173 [patent_doc_number] => 20050272248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Low-k dielectric structure and method' [patent_app_type] => utility [patent_app_number] => 11/185190 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7800 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20050272248.pdf [firstpage_image] =>[orig_patent_app_number] => 11185190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185190
Low-k dielectric structure and method Jul 18, 2005 Abandoned
Array ( [id] => 7045667 [patent_doc_number] => 20050250262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Thin-film transistor structure, method for manufacturing the thin-film transistor structure, and display device using the thin-film transistor structure' [patent_app_type] => utility [patent_app_number] => 11/167637 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7922 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250262.pdf [firstpage_image] =>[orig_patent_app_number] => 11167637 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167637
Method for manufacturing a thin-film transistor structure Jun 26, 2005 Issued
Array ( [id] => 5602549 [patent_doc_number] => 20060292894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Gapfill using deposition-etch sequence' [patent_app_type] => utility [patent_app_number] => 11/166357 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292894.pdf [firstpage_image] =>[orig_patent_app_number] => 11166357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/166357
Gapfill using deposition-etch sequence Jun 23, 2005 Issued
Array ( [id] => 5700210 [patent_doc_number] => 20060216895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Power semiconductor device having buried gate bus and process for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/165077 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3424 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20060216895.pdf [firstpage_image] =>[orig_patent_app_number] => 11165077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165077
Power semiconductor device having buried gate bus and process for fabricating the same Jun 22, 2005 Abandoned
Array ( [id] => 5598748 [patent_doc_number] => 20060289092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Heat dissipation device having low melting point alloy coating and a method thereof' [patent_app_type] => utility [patent_app_number] => 11/159257 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1417 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20060289092.pdf [firstpage_image] =>[orig_patent_app_number] => 11159257 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159257
Heat dissipation device having low melting point alloy coating and a method thereof Jun 22, 2005 Abandoned
Array ( [id] => 626997 [patent_doc_number] => 07135380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/165083 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4072 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135380.pdf [firstpage_image] =>[orig_patent_app_number] => 11165083 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/165083
Method for manufacturing semiconductor device Jun 21, 2005 Issued
Array ( [id] => 5760241 [patent_doc_number] => 20060211186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Method for forming gate in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/156287 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2619 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211186.pdf [firstpage_image] =>[orig_patent_app_number] => 11156287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156287
Method for forming a gate in a semiconductor, which prevents gate leaning caused by thermal processing Jun 16, 2005 Issued
Array ( [id] => 817443 [patent_doc_number] => 07411251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Self protecting NLDMOS, DMOS and extended voltage NMOS devices' [patent_app_type] => utility [patent_app_number] => 11/155087 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2132 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411251.pdf [firstpage_image] =>[orig_patent_app_number] => 11155087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/155087
Self protecting NLDMOS, DMOS and extended voltage NMOS devices Jun 16, 2005 Issued
Array ( [id] => 6966633 [patent_doc_number] => 20050233530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Enhanced gate structure' [patent_app_type] => utility [patent_app_number] => 11/154747 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 848 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20050233530.pdf [firstpage_image] =>[orig_patent_app_number] => 11154747 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/154747
Enhanced gate structure Jun 14, 2005 Abandoned
Array ( [id] => 314755 [patent_doc_number] => 07524725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Vertical transistor of semiconductor device and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/152097 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2162 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524725.pdf [firstpage_image] =>[orig_patent_app_number] => 11152097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152097
Vertical transistor of semiconductor device and method for forming the same Jun 14, 2005 Issued
Array ( [id] => 7229699 [patent_doc_number] => 20050255625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Image sensor with deep well region and method of fabricating the image sensor' [patent_app_type] => utility [patent_app_number] => 11/152364 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7667 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20050255625.pdf [firstpage_image] =>[orig_patent_app_number] => 11152364 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/152364
Image sensor with deep well region and method of fabricating the image sensor Jun 13, 2005 Issued
Array ( [id] => 5776898 [patent_doc_number] => 20060105538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Method for forming semiconductor device capable of preventing bunker defect' [patent_app_type] => utility [patent_app_number] => 11/149297 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3312 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20060105538.pdf [firstpage_image] =>[orig_patent_app_number] => 11149297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149297
Method for forming semiconductor device capable of preventing bunker defect Jun 9, 2005 Issued
Array ( [id] => 6949780 [patent_doc_number] => 20050224874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Forming a retrograde well in a transistor to enhance performance of the transistor' [patent_app_type] => utility [patent_app_number] => 11/148805 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2949 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224874.pdf [firstpage_image] =>[orig_patent_app_number] => 11148805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148805
Forming a retrograde well in a transistor to enhance performance of the transistor Jun 8, 2005 Issued
Array ( [id] => 7056090 [patent_doc_number] => 20050277265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Methods of forming trench isolation layers using high density plasma chemical vapor deposition' [patent_app_type] => utility [patent_app_number] => 11/149307 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20050277265.pdf [firstpage_image] =>[orig_patent_app_number] => 11149307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149307
Methods of forming trench isolation layers using high density plasma chemical vapor deposition Jun 8, 2005 Issued
Array ( [id] => 525111 [patent_doc_number] => 07183145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/148400 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 89 [patent_no_of_words] => 28910 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183145.pdf [firstpage_image] =>[orig_patent_app_number] => 11148400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148400
Semiconductor device and manufacturing method thereof Jun 7, 2005 Issued
Array ( [id] => 482613 [patent_doc_number] => 07220643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'System and method for gate formation in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/147207 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220643.pdf [firstpage_image] =>[orig_patent_app_number] => 11147207 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147207
System and method for gate formation in a semiconductor device Jun 7, 2005 Issued
Array ( [id] => 7019556 [patent_doc_number] => 20050221575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Novel method to fabricate high reliable metal capacitor within copper back-end process' [patent_app_type] => utility [patent_app_number] => 11/143229 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3666 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221575.pdf [firstpage_image] =>[orig_patent_app_number] => 11143229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/143229
Method to fabricate high reliable metal capacitor within copper back-end process Jun 1, 2005 Issued
Array ( [id] => 8538281 [patent_doc_number] => 08314002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Semiconductor device having increased switching speed' [patent_app_type] => utility [patent_app_number] => 11/144727 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2573 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11144727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/144727
Semiconductor device having increased switching speed Jun 1, 2005 Issued
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