
Toniae M. Thomas
Examiner (ID: 17248)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 1104, 1763, 2822, 2813 |
| Total Applications | 1101 |
| Issued Applications | 969 |
| Pending Applications | 9 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 314759
[patent_doc_number] => 07524729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Method of manufacturing a semiconductor integrated circuit device having a trench'
[patent_app_type] => utility
[patent_app_number] => 11/189833
[patent_app_country] => US
[patent_app_date] => 2005-07-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/524/07524729.pdf
[firstpage_image] =>[orig_patent_app_number] => 11189833
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/189833 | Method of manufacturing a semiconductor integrated circuit device having a trench | Jul 26, 2005 | Issued |
Array
(
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[patent_doc_number] => 07244644
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[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Undercut and residual spacer prevention for dual stressed layers'
[patent_app_type] => utility
[patent_app_number] => 11/161067
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[patent_app_date] => 2005-07-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161067 | Undercut and residual spacer prevention for dual stressed layers | Jul 20, 2005 | Issued |
Array
(
[id] => 7248173
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[patent_issue_date] => 2005-12-08
[patent_title] => 'Low-k dielectric structure and method'
[patent_app_type] => utility
[patent_app_number] => 11/185190
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[patent_app_date] => 2005-07-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185190 | Low-k dielectric structure and method | Jul 18, 2005 | Abandoned |
Array
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[patent_issue_date] => 2005-11-10
[patent_title] => 'Thin-film transistor structure, method for manufacturing the thin-film transistor structure, and display device using the thin-film transistor structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/167637 | Method for manufacturing a thin-film transistor structure | Jun 26, 2005 | Issued |
Array
(
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[patent_issue_date] => 2006-12-28
[patent_title] => 'Gapfill using deposition-etch sequence'
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Array
(
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[patent_title] => 'Power semiconductor device having buried gate bus and process for fabricating the same'
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Array
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[patent_title] => 'Heat dissipation device having low melting point alloy coating and a method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/159257 | Heat dissipation device having low melting point alloy coating and a method thereof | Jun 22, 2005 | Abandoned |
Array
(
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[patent_title] => 'Method for manufacturing semiconductor device'
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[patent_app_number] => 11/165083
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Array
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[id] => 5760241
[patent_doc_number] => 20060211186
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[patent_issue_date] => 2006-09-21
[patent_title] => 'Method for forming gate in semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/156287 | Method for forming a gate in a semiconductor, which prevents gate leaning caused by thermal processing | Jun 16, 2005 | Issued |
Array
(
[id] => 817443
[patent_doc_number] => 07411251
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[patent_issue_date] => 2008-08-12
[patent_title] => 'Self protecting NLDMOS, DMOS and extended voltage NMOS devices'
[patent_app_type] => utility
[patent_app_number] => 11/155087
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/155087 | Self protecting NLDMOS, DMOS and extended voltage NMOS devices | Jun 16, 2005 | Issued |
Array
(
[id] => 6966633
[patent_doc_number] => 20050233530
[patent_country] => US
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[patent_issue_date] => 2005-10-20
[patent_title] => 'Enhanced gate structure'
[patent_app_type] => utility
[patent_app_number] => 11/154747
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/154747 | Enhanced gate structure | Jun 14, 2005 | Abandoned |
Array
(
[id] => 314755
[patent_doc_number] => 07524725
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[patent_title] => 'Vertical transistor of semiconductor device and method for forming the same'
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Array
(
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[patent_title] => 'Image sensor with deep well region and method of fabricating the image sensor'
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Array
(
[id] => 5776898
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Array
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Array
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Array
(
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Array
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