
Toniae M. Thomas
Examiner (ID: 17248)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 1104, 1763, 2822, 2813 |
| Total Applications | 1101 |
| Issued Applications | 969 |
| Pending Applications | 9 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 677057
[patent_doc_number] => 07087952
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Dual function FinFET, finmemory and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/978951
[patent_app_country] => US
[patent_app_date] => 2004-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 41
[patent_no_of_words] => 4695
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/087/07087952.pdf
[firstpage_image] =>[orig_patent_app_number] => 10978951
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/978951 | Dual function FinFET, finmemory and method of manufacture | Oct 31, 2004 | Issued |
Array
(
[id] => 7252850
[patent_doc_number] => 20050074936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Method of fabricating a semiconductor device including a reaction barrier film, a diffusion barrier film and a ferroelectric film'
[patent_app_type] => utility
[patent_app_number] => 10/968077
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6365
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20050074936.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968077
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968077 | Method of fabricating a semiconductor device including a reaction barrier film, a diffusion barrier film and a ferroelectric film | Oct 19, 2004 | Abandoned |
Array
(
[id] => 5715683
[patent_doc_number] => 20060079046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'METHOD AND STRUCTURE FOR IMPROVING CMOS DEVICE RELIABILITY USING COMBINATIONS OF INSULATING MATERIALS'
[patent_app_type] => utility
[patent_app_number] => 10/711897
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2246
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20060079046.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711897
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711897 | METHOD AND STRUCTURE FOR IMPROVING CMOS DEVICE RELIABILITY USING COMBINATIONS OF INSULATING MATERIALS | Oct 11, 2004 | Abandoned |
Array
(
[id] => 522551
[patent_doc_number] => 07190063
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Semiconductor device and method of manufacturing the same, circuit board, and electronic apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/962157
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 6788
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190063.pdf
[firstpage_image] =>[orig_patent_app_number] => 10962157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/962157 | Semiconductor device and method of manufacturing the same, circuit board, and electronic apparatus | Oct 7, 2004 | Issued |
Array
(
[id] => 7204028
[patent_doc_number] => 20050042859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Etching process for high-k gate dielectrics'
[patent_app_type] => utility
[patent_app_number] => 10/961707
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2830
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20050042859.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961707 | Etching process for high-k gate dielectrics | Oct 7, 2004 | Abandoned |
Array
(
[id] => 959015
[patent_doc_number] => 06953961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-11
[patent_title] => 'DRAM structure and fabricating method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/711623
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2850
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/953/06953961.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711623 | DRAM structure and fabricating method thereof | Sep 28, 2004 | Issued |
Array
(
[id] => 485531
[patent_doc_number] => 07217619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Method for fabricating memory components'
[patent_app_type] => utility
[patent_app_number] => 10/954157
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2348
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217619.pdf
[firstpage_image] =>[orig_patent_app_number] => 10954157
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/954157 | Method for fabricating memory components | Sep 28, 2004 | Issued |
Array
(
[id] => 6971864
[patent_doc_number] => 20050037574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Semiconductor memory device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/950456
[patent_app_country] => US
[patent_app_date] => 2004-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5990
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20050037574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10950456
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/950456 | Semiconductor memory device and manufacturing method thereof | Sep 27, 2004 | Issued |
Array
(
[id] => 534171
[patent_doc_number] => 07172936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-06
[patent_title] => 'Method to selectively strain NMOS devices using a cap poly layer'
[patent_app_type] => utility
[patent_app_number] => 10/949447
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5471
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/172/07172936.pdf
[firstpage_image] =>[orig_patent_app_number] => 10949447
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/949447 | Method to selectively strain NMOS devices using a cap poly layer | Sep 23, 2004 | Issued |
Array
(
[id] => 7605438
[patent_doc_number] => 07115491
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-03
[patent_title] => 'Method for forming self-aligned contact in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/940707
[patent_app_country] => US
[patent_app_date] => 2004-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 2472
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/115/07115491.pdf
[firstpage_image] =>[orig_patent_app_number] => 10940707
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/940707 | Method for forming self-aligned contact in semiconductor device | Sep 14, 2004 | Issued |
Array
(
[id] => 843485
[patent_doc_number] => 07387927
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-17
[patent_title] => 'Reducing oxidation under a high K gate dielectric'
[patent_app_type] => utility
[patent_app_number] => 10/939227
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2974
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/387/07387927.pdf
[firstpage_image] =>[orig_patent_app_number] => 10939227
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/939227 | Reducing oxidation under a high K gate dielectric | Sep 9, 2004 | Issued |
Array
(
[id] => 7033817
[patent_doc_number] => 20050032327
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium'
[patent_app_type] => utility
[patent_app_number] => 10/936684
[patent_app_country] => US
[patent_app_date] => 2004-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 7943
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20050032327.pdf
[firstpage_image] =>[orig_patent_app_number] => 10936684
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/936684 | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium | Sep 8, 2004 | Issued |
Array
(
[id] => 224850
[patent_doc_number] => 07605033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-10-20
[patent_title] => 'Low resistance peripheral local interconnect contacts with selective wet strip of titanium'
[patent_app_type] => utility
[patent_app_number] => 10/932327
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5457
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/605/07605033.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932327
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932327 | Low resistance peripheral local interconnect contacts with selective wet strip of titanium | Aug 31, 2004 | Issued |
Array
(
[id] => 5903465
[patent_doc_number] => 20060046390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'DUAL-BIT NON-VOLATILE MEMORY CELL AND METHOD OF MAKING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 10/711197
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1740
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20060046390.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711197
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711197 | Dual-bit non-volatile memory cell and method of making the same | Aug 31, 2004 | Issued |
Array
(
[id] => 7025651
[patent_doc_number] => 20050020045
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'Semiconductor device having a low-resistance gate electrode'
[patent_app_type] => utility
[patent_app_number] => 10/926133
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4976
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0020/20050020045.pdf
[firstpage_image] =>[orig_patent_app_number] => 10926133
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/926133 | Semiconductor device having a low-resistance gate electrode | Aug 24, 2004 | Issued |
Array
(
[id] => 461312
[patent_doc_number] => 07242073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-10
[patent_title] => 'Capacitor having an anodic metal oxide substrate'
[patent_app_type] => utility
[patent_app_number] => 10/925428
[patent_app_country] => US
[patent_app_date] => 2004-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 26
[patent_no_of_words] => 7388
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/242/07242073.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925428
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925428 | Capacitor having an anodic metal oxide substrate | Aug 23, 2004 | Issued |
Array
(
[id] => 7083344
[patent_doc_number] => 20050048724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Deep submicron manufacturing method for electrostatic discharge protection devices'
[patent_app_type] => utility
[patent_app_number] => 10/922837
[patent_app_country] => US
[patent_app_date] => 2004-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 1777
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20050048724.pdf
[firstpage_image] =>[orig_patent_app_number] => 10922837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/922837 | Deep submicron manufacturing method for electrostatic discharge protection devices | Aug 22, 2004 | Abandoned |
Array
(
[id] => 7149907
[patent_doc_number] => 20050024520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Image sensor having integrated thin film infrared filter'
[patent_app_type] => utility
[patent_app_number] => 10/922211
[patent_app_country] => US
[patent_app_date] => 2004-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2025
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20050024520.pdf
[firstpage_image] =>[orig_patent_app_number] => 10922211
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/922211 | Image sensor having integrated thin film infrared filter | Aug 18, 2004 | Issued |
Array
(
[id] => 891891
[patent_doc_number] => 07344935
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-03-18
[patent_title] => 'Method of manufacturing a semiconductor integrated circuit device'
[patent_app_type] => utility
[patent_app_number] => 10/920247
[patent_app_country] => US
[patent_app_date] => 2004-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5614
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/344/07344935.pdf
[firstpage_image] =>[orig_patent_app_number] => 10920247
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/920247 | Method of manufacturing a semiconductor integrated circuit device | Aug 17, 2004 | Issued |
Array
(
[id] => 7122511
[patent_doc_number] => 20050014340
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Method of manufacturing a semiconductor integrated circuit device having a trench'
[patent_app_type] => utility
[patent_app_number] => 10/919432
[patent_app_country] => US
[patent_app_date] => 2004-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 9370
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0014/20050014340.pdf
[firstpage_image] =>[orig_patent_app_number] => 10919432
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/919432 | Method of manufacturing a semiconductor integrated circuit device having a trench | Aug 16, 2004 | Issued |