Search

Tony Michael Argenbright

Examiner (ID: 16234)

Most Active Art Unit
3402
Art Unit(s)
3747, 3402
Total Applications
2731
Issued Applications
2589
Pending Applications
40
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15905463 [patent_doc_number] => 20200152252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SPIN-ORBIT TORQUE MAGNETORESISTIVE RANDON ACCESS MEMORY AND METHOD AND APPARATUS FOR WRITING THE SAME [patent_app_type] => utility [patent_app_number] => 16/452035 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452035 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452035
SPIN-ORBIT TORQUE MAGNETORESISTIVE RANDON ACCESS MEMORY AND METHOD AND APPARATUS FOR WRITING THE SAME Jun 24, 2019 Abandoned
Array ( [id] => 15298361 [patent_doc_number] => 20190392316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => WEIGHT MATRIX CIRCUIT AND WEIGHT MATRIX INPUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/450968 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450968
Weight matrix circuit and weight matrix input circuit Jun 23, 2019 Issued
Array ( [id] => 16285574 [patent_doc_number] => 20200279176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => 4T4R TERNARY WEIGHT CELL WITH HIGH ON/OFF RATIO BACKGROUND [patent_app_type] => utility [patent_app_number] => 16/448842 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448842
4T4R ternary weight cell with high on/off ratio background Jun 20, 2019 Issued
Array ( [id] => 15299535 [patent_doc_number] => 20190392903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => NON-VOLATILE MEMORY DEVICE, MICROCOMPUTER, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/447191 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447191
NON-VOLATILE MEMORY DEVICE, MICROCOMPUTER, AND ELECTRONIC DEVICE Jun 19, 2019 Abandoned
Array ( [id] => 16515829 [patent_doc_number] => 20200395087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SOFT ERASE AND PROGRAMMING OF NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/440631 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440631 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440631
Soft erase and programming of nonvolatile memory Jun 12, 2019 Issued
Array ( [id] => 15938585 [patent_doc_number] => 20200160926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => Electrically Programmable Fuse Circuit, Programming Method for Electrically Programmable Fuse, and State Detection Method for Electrically Programmable Fuse [patent_app_type] => utility [patent_app_number] => 16/423923 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423923
Electrically programmable fuse circuit, programming method for electrically programmable fuse, and state detection method for electrically programmable fuse May 27, 2019 Issued
Array ( [id] => 14874771 [patent_doc_number] => 20190287627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH [patent_app_type] => utility [patent_app_number] => 16/412269 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412269
Erase and soft program for vertical NAND flash May 13, 2019 Issued
Array ( [id] => 16379094 [patent_doc_number] => 20200327937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => ReRAM MEMORY CELL HAVING DUAL WORD LINE CONTROL [patent_app_type] => utility [patent_app_number] => 16/405895 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405895
ReRAM memory cell having dual word line control May 6, 2019 Issued
Array ( [id] => 16402063 [patent_doc_number] => 20200342921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => THREE-PORT MEMORY CELL AND ARRAY FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 16/393997 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/393997
Three-port memory cell and array for in-memory computing Apr 24, 2019 Issued
Array ( [id] => 16379099 [patent_doc_number] => 20200327942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => CONTENT ADDRESSABLE MEMORY SYSTEMS WITH CONTENT ADDRESSABLE MEMORY BUFFERS [patent_app_type] => utility [patent_app_number] => 16/382449 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382449
Content addressable memory systems with content addressable memory buffers Apr 11, 2019 Issued
Array ( [id] => 16347761 [patent_doc_number] => 20200312412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => CURRENT MONITORING IN SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/371221 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371221
Current monitoring in semiconductor packages Mar 31, 2019 Issued
Array ( [id] => 16552786 [patent_doc_number] => 10885950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device [patent_app_type] => utility [patent_app_number] => 16/363077 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363077 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363077
Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device Mar 24, 2019 Issued
Array ( [id] => 14584731 [patent_doc_number] => 20190219974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => GLOVE SYSTEM FOR REMOTE CONTROL OF INDUSTRIAL MACHINES [patent_app_type] => utility [patent_app_number] => 16/362178 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362178
Glove system for remote control of industrial machines Mar 21, 2019 Issued
Array ( [id] => 14584733 [patent_doc_number] => 20190219975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => METHOD FOR CONTROLLING AN INDUSTRIAL MACHINE WITH A GLOVE DEVICE [patent_app_type] => utility [patent_app_number] => 16/362291 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362291
Method for controlling an industrial machine with a glove device Mar 21, 2019 Issued
Array ( [id] => 16653168 [patent_doc_number] => 10930359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Programmable read-only memory having at least four memory cells, each having switching element and data storage element arranged so that each switching element is connected to at least two selection lines and the storage elements are shared by a data line [patent_app_type] => utility [patent_app_number] => 16/356217 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356217
Programmable read-only memory having at least four memory cells, each having switching element and data storage element arranged so that each switching element is connected to at least two selection lines and the storage elements are shared by a data line Mar 17, 2019 Issued
Array ( [id] => 14541743 [patent_doc_number] => 20190206493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH A PLURALITY OF MEMORY BLOCKS AND A SHARED BLOCK DECODER [patent_app_type] => utility [patent_app_number] => 16/295620 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295620
Nonvolatile semiconductor memory device with a plurality of memory blocks and a shared block decoder Mar 6, 2019 Issued
Array ( [id] => 16834964 [patent_doc_number] => 11011222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Memory structure with bitline strapping [patent_app_type] => utility [patent_app_number] => 16/294577 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5430 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294577
Memory structure with bitline strapping Mar 5, 2019 Issued
Array ( [id] => 15217441 [patent_doc_number] => 20190371407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/291163 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291163 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291163
Semiconductor memory including plural memory blocks, a sequencer that controls a driver, a row decoder, and sense amplifier modules based on commands held in a command register to perform read, write, erase Mar 3, 2019 Issued
Array ( [id] => 15702973 [patent_doc_number] => 10607673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Semiconductor devices for controlling input of a data strobe signal [patent_app_type] => utility [patent_app_number] => 16/284425 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6491 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16284425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/284425
Semiconductor devices for controlling input of a data strobe signal Feb 24, 2019 Issued
Array ( [id] => 16631399 [patent_doc_number] => 20210050052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/968922 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16968922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/968922
Memory device and method of operating the same Feb 12, 2019 Issued
Menu