Search

Tony Michael Argenbright

Examiner (ID: 16234)

Most Active Art Unit
3402
Art Unit(s)
3747, 3402
Total Applications
2731
Issued Applications
2589
Pending Applications
40
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16047621 [patent_doc_number] => 10685689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/259259 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9559 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259259
Semiconductor memory device Jan 27, 2019 Issued
Array ( [id] => 14347577 [patent_doc_number] => 20190155761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => Multiprocessor System with Improved Secondary Interconnection Network [patent_app_type] => utility [patent_app_number] => 16/252827 [patent_app_country] => US [patent_app_date] => 2019-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252827
Multiprocessor system with improved secondary interconnection network Jan 20, 2019 Issued
Array ( [id] => 16162697 [patent_doc_number] => 20200219581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => CONFIGURABLE POST-PACKAGE REPAIR [patent_app_type] => utility [patent_app_number] => 16/239117 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239117
Configurable post-package repair Jan 2, 2019 Issued
Array ( [id] => 14842629 [patent_doc_number] => 20190279715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => APPARATUS AND METHODS INCLUDING SOURCE GATES [patent_app_type] => utility [patent_app_number] => 16/237337 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237337 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237337
Apparatus and methods including source gates Dec 30, 2018 Issued
Array ( [id] => 16034565 [patent_doc_number] => 10679709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Method for reading data stored in a flash memory according to a voltage characteristic and memory controller thereof [patent_app_type] => utility [patent_app_number] => 16/228007 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8043 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228007
Method for reading data stored in a flash memory according to a voltage characteristic and memory controller thereof Dec 19, 2018 Issued
Array ( [id] => 16080129 [patent_doc_number] => 20200194051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => APPARATUSES FOR DECREASING WRITE PULL-UP TIME AND METHODS OF USE [patent_app_type] => utility [patent_app_number] => 16/218237 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218237 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218237
Apparatuses for decreasing write pull-up time and methods of use Dec 11, 2018 Issued
Array ( [id] => 14163569 [patent_doc_number] => 20190108887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => FLASH STORAGE DEVICE WITH DATA INTEGRITY PROTECTION [patent_app_type] => utility [patent_app_number] => 16/216904 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216904
Flash storage device with data integrity protection Dec 10, 2018 Issued
Array ( [id] => 15856763 [patent_doc_number] => 10643674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Invert operations using sensing circuitry [patent_app_type] => utility [patent_app_number] => 16/192536 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192536 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192536
Invert operations using sensing circuitry Nov 14, 2018 Issued
Array ( [id] => 15487981 [patent_doc_number] => 10559345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-11 [patent_title] => Address decoding circuit performing a multi-bit shift operation in a single clock cycle [patent_app_type] => utility [patent_app_number] => 16/191356 [patent_app_country] => US [patent_app_date] => 2018-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16191356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/191356
Address decoding circuit performing a multi-bit shift operation in a single clock cycle Nov 13, 2018 Issued
Array ( [id] => 15286061 [patent_doc_number] => 10515699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Error handling for match action unit memory of a forwarding element [patent_app_type] => utility [patent_app_number] => 16/181095 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181095
Error handling for match action unit memory of a forwarding element Nov 4, 2018 Issued
Array ( [id] => 14676017 [patent_doc_number] => 20190237123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => PSEUDO STATIC RANDOM ACCESS MEMORY AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/177461 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177461 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177461
Pseudo static random access memory and control method thereof Oct 31, 2018 Issued
Array ( [id] => 16566633 [patent_doc_number] => 10892007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Variable delay word line enable [patent_app_type] => utility [patent_app_number] => 16/171909 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171909
Variable delay word line enable Oct 25, 2018 Issued
Array ( [id] => 15060973 [patent_doc_number] => 10460798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Memory cells having a plurality of resistance variable materials [patent_app_type] => utility [patent_app_number] => 16/158353 [patent_app_country] => US [patent_app_date] => 2018-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/158353
Memory cells having a plurality of resistance variable materials Oct 11, 2018 Issued
Array ( [id] => 13874571 [patent_doc_number] => 20190033626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => DISPLAY DEVICE AND DRIVING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/149720 [patent_app_country] => US [patent_app_date] => 2018-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149720
Display device and driving method thereof Oct 1, 2018 Issued
Array ( [id] => 15717117 [patent_doc_number] => 20200105326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Defect Propagation Structure and Mechanism for Magnetic Memory [patent_app_type] => utility [patent_app_number] => 16/147283 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147283 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147283
Defect propagation structure and mechanism for magnetic memory Sep 27, 2018 Issued
Array ( [id] => 16356229 [patent_doc_number] => 10796746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Frequency synthesis for memory input-output operations [patent_app_type] => utility [patent_app_number] => 16/138621 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138621
Frequency synthesis for memory input-output operations Sep 20, 2018 Issued
Array ( [id] => 14903755 [patent_doc_number] => 20190295643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/128439 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128439
SEMICONDUCTOR MEMORY DEVICE Sep 10, 2018 Abandoned
Array ( [id] => 18262908 [patent_doc_number] => 11610615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit [patent_app_type] => utility [patent_app_number] => 17/274099 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17274099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/274099
Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit Sep 6, 2018 Issued
Array ( [id] => 16372164 [patent_doc_number] => 10803930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system including a memory controller and error correction circuit for reading multi-bit data and for detecting and correcting read data errors [patent_app_type] => utility [patent_app_number] => 16/123123 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 13135 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123123
Memory system including a memory controller and error correction circuit for reading multi-bit data and for detecting and correcting read data errors Sep 5, 2018 Issued
Array ( [id] => 15597065 [patent_doc_number] => 20200075067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFIED MISMATCHES [patent_app_type] => utility [patent_app_number] => 16/121325 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121325
Apparatuses and method for trimming input buffers based on identified mismatches Sep 3, 2018 Issued
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