Tony Michael Argenbright

Array ( [id] => 19951098 [patent_doc_number] => 12322468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Conditional write back scheme for memory [patent_app_type] => utility [patent_app_number] => 17/826063 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18488135 [patent_doc_number] => 20230215483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/748471 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18008913 [patent_doc_number] => 20220367680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/740669 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17833363 [patent_doc_number] => 20220270667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MEMORY CELL BIASING TECHNIQUES DURING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 17/741136 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17810599 [patent_doc_number] => 20220262434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => ReRAM Memory Array [patent_app_type] => utility [patent_app_number] => 17/736563 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19341288 [patent_doc_number] => 12051483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Semiconductor memory device including memory string and plurality of select transistors and method including a write operation [patent_app_type] => utility [patent_app_number] => 17/729114 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9602 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18024023 [patent_doc_number] => 20220375522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => COPY REDUNDANCY IN A KEY-VALUE DATA STORAGE SYSTEM USING CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/729989 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19934880 [patent_doc_number] => 12308088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Sense amplifier including pre-amplifying circuit and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/660232 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18322687 [patent_doc_number] => 20230120815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => REFRESH CIRCUIT, REFRESH METHOD AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/658287 [patent_app_country] => US [patent_app_date] => 2022-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18679510 [patent_doc_number] => 20230317166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ANALOG CONTENT-ADDRESS MEMORY HAVING APPROXIMATION MATCHING AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/711073 [patent_app_country] => US [patent_app_date] => 2022-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18039718 [patent_doc_number] => 20220383935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER [patent_app_type] => utility [patent_app_number] => 17/707034 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18631514 [patent_doc_number] => 20230290416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MEMORY AND READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/693411 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18165222 [patent_doc_number] => 20230031820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => POWER SUPPLY CIRCUIT OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHOD FOR ADJUSTING OPERATION VOLTAGE OF DEVICE [patent_app_type] => utility [patent_app_number] => 17/685941 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19459941 [patent_doc_number] => 12100442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Flash memory device configured to be bonded to external semiconductor chip and computing device including flash memory device coupled to neural processor chip [patent_app_type] => utility [patent_app_number] => 17/682100 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18585713 [patent_doc_number] => 20230267977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SIGNAL DEVELOPMENT CIRCUITRY LAYOUTS IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/680006 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18585707 [patent_doc_number] => 20230267971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SYSTEMS AND METHODS FOR IMPROVED DUAL-TAIL LATCH WITH WIDE INPUT COMMON MODE RANGE [patent_app_type] => utility [patent_app_number] => 17/677628 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17677628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19507621 [patent_doc_number] => 12119050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Variable delay word line enable [patent_app_type] => utility [patent_app_number] => 17/670704 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18688138 [patent_doc_number] => 11783881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Apparatuses, systems, and methods for direct refresh management commands [patent_app_type] => utility [patent_app_number] => 17/666302 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17666302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17615086 [patent_doc_number] => 20220157366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SYSTEMS AND METHODS FOR CAPTURE AND REPLACEMENT OF HAMMERED WORD LINE ADDRESS [patent_app_type] => utility [patent_app_number] => 17/591302 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19093691 [patent_doc_number] => 11955155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Nonvolatile memory device and latch including the same [patent_app_type] => utility [patent_app_number] => 17/588180 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 5840 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588180 [rel_patent_id] =>[rel_patent_doc_number] =>)