Tony Michael Argenbright

Array ( [id] => 18164425 [patent_doc_number] => 20230031020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/536607 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18276878 [patent_doc_number] => 11615824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Serializer and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/536282 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 14323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18464158 [patent_doc_number] => 11688451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking [patent_app_type] => utility [patent_app_number] => 17/456849 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593096 [patent_doc_number] => 11742005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Selectively cross-coupled inverters, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/456819 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12950 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18890802 [patent_doc_number] => 11869579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Page buffer circuit and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/530911 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18857033 [patent_doc_number] => 11854624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Non-volatile memory device and erasing operation method thereof [patent_app_type] => utility [patent_app_number] => 17/530422 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6548 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18124475 [patent_doc_number] => 20230010087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/523195 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19427947 [patent_doc_number] => 12087375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Apparatus and method of performing erase and erase verify operations [patent_app_type] => utility [patent_app_number] => 17/519676 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18155928 [patent_doc_number] => 11568917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-31 [patent_title] => Hammer refresh row address detector, and semiconductor memory device and memory module including the same [patent_app_type] => utility [patent_app_number] => 17/504705 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19639502 [patent_doc_number] => 12170115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Write performance optimization for erase on demand [patent_app_type] => utility [patent_app_number] => 17/451479 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18306308 [patent_doc_number] => 20230110208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR ZQ CALIBRATION [patent_app_type] => utility [patent_app_number] => 17/449861 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18918995 [patent_doc_number] => 11881283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Semiconductor memory device and memory system including memory cell arrays and column selection transistors arranged to improve size efficiency [patent_app_type] => utility [patent_app_number] => 17/492336 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18306970 [patent_doc_number] => 20230110870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => REGULATOR OF A SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/490976 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19765974 [patent_doc_number] => 12224275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => TSV check circuit with replica path [patent_app_type] => utility [patent_app_number] => 17/489502 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18280666 [patent_doc_number] => 20230096138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => ENCODED ENABLE CLOCK GATERS [patent_app_type] => utility [patent_app_number] => 17/485178 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18455873 [patent_doc_number] => 20230197154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => STATIC RANDOM-ACCESS MEMORY (SRAM) CELL FOR HIGH-SPEED CONTENT-ADDRESSABLE MEMORY AND IN-MEMORY BOOLEAN LOGIC OPERATION [patent_app_type] => utility [patent_app_number] => 17/802968 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17802968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19370303 [patent_doc_number] => 12062393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Nonvolatile semiconductor memory device with a plurality of memory blocks and a shared block decoder [patent_app_type] => utility [patent_app_number] => 17/471597 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14303 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 558 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19079250 [patent_doc_number] => 11948625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Systems on chips, memory circuits, and methods for accessing data in a memory circuit directly using a transistor-level operation signal [patent_app_type] => utility [patent_app_number] => 17/471073 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18031775 [patent_doc_number] => 11514970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Memory device and method having a control circuit configured to acquire information on a state of a control target, causes the control target to execute a read and write operation based on the state [patent_app_type] => utility [patent_app_number] => 17/470802 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 20923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18240570 [patent_doc_number] => 20230072881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS [patent_app_type] => utility [patent_app_number] => 17/468588 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468588 [rel_patent_id] =>[rel_patent_doc_number] =>)