Search

Tony Michael Argenbright

Examiner (ID: 16234)

Most Active Art Unit
3402
Art Unit(s)
3747, 3402
Total Applications
2731
Issued Applications
2589
Pending Applications
40
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18226609 [patent_doc_number] => 20230065603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => PRE-COMPARE OPERATION FOR COMPACT LOW-LEAKAGE DUAL-COMPARE CAM CELL [patent_app_type] => utility [patent_app_number] => 17/462659 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462659
Pre-compare operation for compact low-leakage dual-compare cam cell Aug 30, 2021 Issued
Array ( [id] => 18782004 [patent_doc_number] => 11823769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Reducing capacitive loading of memory system based on switches [patent_app_type] => utility [patent_app_number] => 17/460216 [patent_app_country] => US [patent_app_date] => 2021-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460216 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460216
Reducing capacitive loading of memory system based on switches Aug 27, 2021 Issued
Array ( [id] => 18212674 [patent_doc_number] => 20230058938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => PROBABILISTIC COMPUTING DEVICES BASED ON STOCHASTIC SWITCHING IN A FERROELECTRIC FIELD-EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/409483 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409483
Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor Aug 22, 2021 Issued
Array ( [id] => 19539242 [patent_doc_number] => 12131797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Data transmission circuit, data transmission method and memory device [patent_app_type] => utility [patent_app_number] => 17/769934 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17769934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/769934
Data transmission circuit, data transmission method and memory device Aug 11, 2021 Issued
Array ( [id] => 19672742 [patent_doc_number] => 12185538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor memory device with a three-dimensional stacked memory cell structure [patent_app_type] => utility [patent_app_number] => 17/398654 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 4546 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398654
Semiconductor memory device with a three-dimensional stacked memory cell structure Aug 9, 2021 Issued
Array ( [id] => 18639285 [patent_doc_number] => 11763901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Nonvolatile memory device and method of detecting defective memory cell block of nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/397012 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397012
Nonvolatile memory device and method of detecting defective memory cell block of nonvolatile memory device Aug 8, 2021 Issued
Array ( [id] => 18721257 [patent_doc_number] => 11798609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Semiconductor memory device including control unit controlling time interval of refresh operation on memory to shorten interval between memory refresh operations corresponding to read/write access requirement [patent_app_type] => utility [patent_app_number] => 17/395667 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 10617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395667
Semiconductor memory device including control unit controlling time interval of refresh operation on memory to shorten interval between memory refresh operations corresponding to read/write access requirement Aug 5, 2021 Issued
Array ( [id] => 17373397 [patent_doc_number] => 20220028449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => CIRCUITS FOR POWER DOWN LEAKAGE REDUCTION IN RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/443480 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443480
Circuits for power down leakage reduction in random-access memory Jul 26, 2021 Issued
Array ( [id] => 17582618 [patent_doc_number] => 20220139473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => NON-VOLATILE MEMORY DEVICE FOR PERFORMING PRECHARGE TO CELL STRING AND PROGRAM METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/385493 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385493
Non-volatile memory device for performing precharge to cell string and program method thereof Jul 25, 2021 Issued
Array ( [id] => 17917166 [patent_doc_number] => 20220319562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => ELECTRONIC DEVICE FOR PERFORMING READ OPERATION USING PIPE CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/375400 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375400
Electronic device for performing read operation using pipe circuit Jul 13, 2021 Issued
Array ( [id] => 17203243 [patent_doc_number] => 20210343338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => OVERWRITE READ METHODS FOR RESISTANCE SWITCHING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/375993 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375993
Overwrite read methods for resistance switching memory devices Jul 13, 2021 Issued
Array ( [id] => 18304243 [patent_doc_number] => 11626155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Memory and operation method having a random seed generation circuit, random signal generator, and an address sampling circuit for sampling active address [patent_app_type] => utility [patent_app_number] => 17/365506 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365506
Memory and operation method having a random seed generation circuit, random signal generator, and an address sampling circuit for sampling active address Jun 30, 2021 Issued
Array ( [id] => 17833368 [patent_doc_number] => 20220270672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/365462 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365462
Semiconductor memory device for performing target refresh operation and hidden refresh operation in response to normal refresh command and determining row hammer risk level Jun 30, 2021 Issued
Array ( [id] => 17173843 [patent_doc_number] => 20210327514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => ERASE CYCLE HEALING USING A HIGH VOLTAGE PULSE [patent_app_type] => utility [patent_app_number] => 17/361259 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361259
Erase cycle healing using a high voltage pulse Jun 27, 2021 Issued
Array ( [id] => 19229378 [patent_doc_number] => 12009019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Non-volatile associative memory cell, non-volatile associative memory device, monitoring method, and non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 17/358872 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 32559 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358872
Non-volatile associative memory cell, non-volatile associative memory device, monitoring method, and non-volatile memory cell Jun 24, 2021 Issued
Array ( [id] => 18120342 [patent_doc_number] => 11551740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor memory device and refresh operation method, including input circuit, plurality of latches, plurality of counters and refresh controller for generating reset signals [patent_app_type] => utility [patent_app_number] => 17/353004 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9634 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353004
Semiconductor memory device and refresh operation method, including input circuit, plurality of latches, plurality of counters and refresh controller for generating reset signals Jun 20, 2021 Issued
Array ( [id] => 18080746 [patent_doc_number] => 20220406358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CONCURRENT COMPENSATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/350305 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350305
Concurrent compensation in a memory system Jun 16, 2021 Issued
Array ( [id] => 18080743 [patent_doc_number] => 20220406355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CELL DISTURB ON POWER STATE TRANSITION [patent_app_type] => utility [patent_app_number] => 17/350771 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350771
Cell disturb on power state transition Jun 16, 2021 Issued
Array ( [id] => 17764538 [patent_doc_number] => 20220238151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => IN-MEMORY COMPUTATION DEVICE AND IN-MEMORY COMPUTATION METHOD [patent_app_type] => utility [patent_app_number] => 17/344555 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/344555
In-memory computation device and in-memory computation method to perform multiplication operation in memory cell array according to bit orders Jun 9, 2021 Issued
Array ( [id] => 18205227 [patent_doc_number] => 11587629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Detecting latent defects in a memory device during an erase operation based on physical and logical segment fail bits [patent_app_type] => utility [patent_app_number] => 17/341814 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 15075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341814 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341814
Detecting latent defects in a memory device during an erase operation based on physical and logical segment fail bits Jun 7, 2021 Issued
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