Search

Tony Michael Argenbright

Examiner (ID: 16234)

Most Active Art Unit
3402
Art Unit(s)
3747, 3402
Total Applications
2731
Issued Applications
2589
Pending Applications
40
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17978400 [patent_doc_number] => 11495272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Electronic device configured to perform an auto-precharge operation [patent_app_type] => utility [patent_app_number] => 17/158413 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15199 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158413
Electronic device configured to perform an auto-precharge operation Jan 25, 2021 Issued
Array ( [id] => 17925674 [patent_doc_number] => 11468933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Content addressable memory, data processing method, and network device [patent_app_type] => utility [patent_app_number] => 17/156938 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 18339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156938
Content addressable memory, data processing method, and network device Jan 24, 2021 Issued
Array ( [id] => 18053889 [patent_doc_number] => 11527280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Monitoring and mitigation of row disturbance in memory [patent_app_type] => utility [patent_app_number] => 17/156182 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156182
Monitoring and mitigation of row disturbance in memory Jan 21, 2021 Issued
Array ( [id] => 17956162 [patent_doc_number] => 11482275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Apparatuses and methods for dynamically allocated aggressor detection [patent_app_type] => utility [patent_app_number] => 17/153555 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153555
Apparatuses and methods for dynamically allocated aggressor detection Jan 19, 2021 Issued
Array ( [id] => 17380891 [patent_doc_number] => 11238912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Magnetoresistive random-access memory [patent_app_type] => utility [patent_app_number] => 17/146424 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146424
Magnetoresistive random-access memory Jan 10, 2021 Issued
Array ( [id] => 16795849 [patent_doc_number] => 20210125666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => ReRAM MEMORY CELL HAVING DUAL WORD LINE CONTROL AND METHOD FOR ERASING A ReRAM MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/140064 [patent_app_country] => US [patent_app_date] => 2021-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140064
Method for erasing a ReRAM memory cell Jan 1, 2021 Issued
Array ( [id] => 17818336 [patent_doc_number] => 11423957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Sense amplifier, memory and method for controlling a sense amplifier [patent_app_type] => utility [patent_app_number] => 17/441679 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7016 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17441679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/441679
Sense amplifier, memory and method for controlling a sense amplifier Dec 24, 2020 Issued
Array ( [id] => 17332236 [patent_doc_number] => 11222704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-11 [patent_title] => Power state aware scan frequency [patent_app_type] => utility [patent_app_number] => 17/125902 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 22525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125902
Power state aware scan frequency Dec 16, 2020 Issued
Array ( [id] => 17676363 [patent_doc_number] => 20220189530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => TERMINALS AND DATA INPUT/OUTPUT CIRCUITS LAYOUT [patent_app_type] => utility [patent_app_number] => 17/119483 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119483
Semiconductor device layout for a plurality of pads and a plurality of data queue circuits Dec 10, 2020 Issued
Array ( [id] => 18008216 [patent_doc_number] => 20220366983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => MEMORY APPARATUS AND METHODS FOR ACCESSING AND MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/597816 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17597816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/597816
Accessing memory cells in a vertical memory array Dec 8, 2020 Issued
Array ( [id] => 18073511 [patent_doc_number] => 11532348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Power management across multiple packages of memory dies [patent_app_type] => utility [patent_app_number] => 17/110128 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 16509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110128
Power management across multiple packages of memory dies Dec 1, 2020 Issued
Array ( [id] => 17309978 [patent_doc_number] => 11211102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device [patent_app_type] => utility [patent_app_number] => 17/104114 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 8342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104114
Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device Nov 24, 2020 Issued
Array ( [id] => 18024022 [patent_doc_number] => 20220375521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => COMPUTER SYSTEM AND METHOD FOR OPERATING DATA PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 17/773887 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17773887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/773887
Computer system using 3D OS NAND Nov 8, 2020 Issued
Array ( [id] => 17878350 [patent_doc_number] => 11450371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Semiconductor device having plurality of 2T2C DRAM memory cells [patent_app_type] => utility [patent_app_number] => 17/086643 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 61 [patent_no_of_words] => 21830 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/086643
Semiconductor device having plurality of 2T2C DRAM memory cells Nov 1, 2020 Issued
Array ( [id] => 17956163 [patent_doc_number] => 11482276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => System and method for read speed improvement in 3T DRAM [patent_app_type] => utility [patent_app_number] => 17/085287 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9686 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085287 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085287
System and method for read speed improvement in 3T DRAM Oct 29, 2020 Issued
Array ( [id] => 16624596 [patent_doc_number] => 20210043249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => VARIABLE DELAY WORD LINE ENABLE [patent_app_type] => utility [patent_app_number] => 17/081214 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081214
Variable delay word line enable Oct 26, 2020 Issued
Array ( [id] => 16795836 [patent_doc_number] => 20210125653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => RACE TRACK MAGNETIC MEMORY DEVICE AND WRITING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/076300 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076300
Race track magnetic memory device and writing method thereof Oct 20, 2020 Issued
Array ( [id] => 17262361 [patent_doc_number] => 20210375346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING ADDRESS GENERATION CIRCUIT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/070131 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070131
Semiconductor memory device having plurality of address storing circuits for storing sampling address as latch addresses and a duplication decision circuit, and method of refreshing operation Oct 13, 2020 Issued
Array ( [id] => 17878355 [patent_doc_number] => 11450376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Word line driver circuits for memory devices and methods of operating same [patent_app_type] => utility [patent_app_number] => 17/038488 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12301 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038488
Word line driver circuits for memory devices and methods of operating same Sep 29, 2020 Issued
Array ( [id] => 19427922 [patent_doc_number] => 12087350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration [patent_app_type] => utility [patent_app_number] => 17/032191 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 8726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/032191
Multi-deck non-volatile memory architecture with improved wordline bus and bitline bus configuration Sep 24, 2020 Issued
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