Search

Tony Tran

Examiner (ID: 13756, Phone: (571)270-1749 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894, 2809, 2821, 2893
Total Applications
1144
Issued Applications
736
Pending Applications
102
Abandoned Applications
312

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13085263 [patent_doc_number] => 10062705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Method of manufacturing a flash memory [patent_app_type] => utility [patent_app_number] => 15/487404 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2584 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487404
Method of manufacturing a flash memory Apr 12, 2017 Issued
Array ( [id] => 15401099 [patent_doc_number] => 10541211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Control warpage in a semiconductor chip package [patent_app_type] => utility [patent_app_number] => 15/486749 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486749
Control warpage in a semiconductor chip package Apr 12, 2017 Issued
Array ( [id] => 12188945 [patent_doc_number] => 20180047880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD OF FABRICATING LIGHT EMITTING DEVICE PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/486982 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486982 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486982
Method of fabricating light emitting device package Apr 12, 2017 Issued
Array ( [id] => 14063981 [patent_doc_number] => 10236295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Method of fabricating semiconductor device using dry etching [patent_app_type] => utility [patent_app_number] => 15/486861 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 80 [patent_figures_cnt] => 80 [patent_no_of_words] => 15914 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15486861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/486861
Method of fabricating semiconductor device using dry etching Apr 12, 2017 Issued
Array ( [id] => 14221001 [patent_doc_number] => 20190122885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS [patent_app_type] => utility [patent_app_number] => 16/093521 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16093521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/093521
GROUP III SEMICONDUCTOR EPITAXY FORMED ON SILICON VIA SINGLE CRYSTAL REN AND REO BUFFER LAYERS Apr 9, 2017 Abandoned
Array ( [id] => 12990052 [patent_doc_number] => 20170345755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SEMICONDUCTOR DEVICE, ELECTRICAL ENERGY MEASUREMENT INSTRUMENT, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/479978 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15479978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/479978
Semiconductor device, electrical energy measurement instrument, and manufacturing method of semiconductor device Apr 4, 2017 Issued
Array ( [id] => 11760235 [patent_doc_number] => 20170207104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'FABRICATION METHOD OF SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/478508 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478508
Fabrication method of semiconductor package Apr 3, 2017 Issued
Array ( [id] => 12294672 [patent_doc_number] => 09935245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Semiconductor light-emitting device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/433167 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433167 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433167
Semiconductor light-emitting device and method for fabricating the same Feb 14, 2017 Issued
Array ( [id] => 11652873 [patent_doc_number] => 20170148774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'PACKAGE-ON-PACKAGE MODULES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/424080 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8347 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424080
PACKAGE-ON-PACKAGE MODULES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME Feb 2, 2017 Abandoned
Array ( [id] => 11652802 [patent_doc_number] => 20170148704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'ELECTRICAL PACKAGE INCLUDING BIMETAL LID' [patent_app_type] => utility [patent_app_number] => 15/419031 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1644 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419031
Electrical package including bimetal lid Jan 29, 2017 Issued
Array ( [id] => 11733003 [patent_doc_number] => 20170194446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'NEUROMORPHIC DEVICE INCLUDING GATING LINES WITH DIFFERENT WIDTHS' [patent_app_type] => utility [patent_app_number] => 15/389068 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389068 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389068
Neuromorphic device including gating lines with different widths Dec 21, 2016 Issued
Array ( [id] => 13667031 [patent_doc_number] => 10163690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => 2-D interconnections for integrated circuits [patent_app_type] => utility [patent_app_number] => 15/389060 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6355 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389060 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389060
2-D interconnections for integrated circuits Dec 21, 2016 Issued
Array ( [id] => 12872596 [patent_doc_number] => 20180182707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SCALABLE EMBEDDED SILICON BRIDGE VIA PILLARS IN LITHOGRAPHICALLY DEFINED VIAS, AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 15/389100 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389100
Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same Dec 21, 2016 Issued
Array ( [id] => 12872626 [patent_doc_number] => 20180182717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => INTEGRATED CIRCUIT DEVICES WITH SELECTIVELY ARRANGED THROUGH SUBSTRATE VIAS AND METHOD OF MANUFACTURE THEREOF [patent_app_type] => utility [patent_app_number] => 15/389252 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389252
Integrated circuit devices with selectively arranged through substrate vias and method of manufacture thereof Dec 21, 2016 Issued
Array ( [id] => 16068159 [patent_doc_number] => 10693046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Chip scale packaging light emitting device and manufacturing method of the same [patent_app_type] => utility [patent_app_number] => 15/389417 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10604 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389417 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389417
Chip scale packaging light emitting device and manufacturing method of the same Dec 21, 2016 Issued
Array ( [id] => 12873277 [patent_doc_number] => 20180182934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => Light Emitting Unit [patent_app_type] => utility [patent_app_number] => 15/389213 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389213
Light Emitting Unit Dec 21, 2016 Abandoned
Array ( [id] => 12650196 [patent_doc_number] => 20180108563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => METHOD OF FABRICATING ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/384940 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384940
Method of fabricating isolation structure Dec 19, 2016 Issued
Array ( [id] => 14526129 [patent_doc_number] => 10340335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Method of forming a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/385137 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7152 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385137
Method of forming a semiconductor device Dec 19, 2016 Issued
Array ( [id] => 11718146 [patent_doc_number] => 20170186645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'METHOD OF PROCESSING WAFER' [patent_app_type] => utility [patent_app_number] => 15/385387 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8322 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385387 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385387
Method of processing wafer Dec 19, 2016 Issued
Array ( [id] => 11714725 [patent_doc_number] => 20170183224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'METHOD OF MAKING A CLOSED CAVITY COMPRISING A FLAP PROTECTING THE CAVITY WHEN IT IS CLOSED' [patent_app_type] => utility [patent_app_number] => 15/385209 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385209
Method of making a closed cavity comprising a flap protecting the cavity when it is closed Dec 19, 2016 Issued
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