Search

Tony Tran

Examiner (ID: 13756, Phone: (571)270-1749 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2818, 2894, 2809, 2821, 2893
Total Applications
1144
Issued Applications
736
Pending Applications
102
Abandoned Applications
312

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17963686 [patent_doc_number] => 20220344267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE INCLUDING A THROUGH-VIA STRUCTURE HAVING A VIA LINER HAVING PROTRUDING PORTIONS [patent_app_type] => utility [patent_app_number] => 17/861700 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861700
Three-dimensional semiconductor device including a through-via structure having a via liner having protruding portions Jul 10, 2022 Issued
Array ( [id] => 19444484 [patent_doc_number] => 12094773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Methods for low resistivity and stress tungsten gap fill [patent_app_type] => utility [patent_app_number] => 17/857341 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857341
Methods for low resistivity and stress tungsten gap fill Jul 4, 2022 Issued
Array ( [id] => 17963913 [patent_doc_number] => 20220344494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 17/849188 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849188
EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Jun 23, 2022 Pending
Array ( [id] => 20637836 [patent_doc_number] => 12598731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory device using semiconductor element [patent_app_type] => utility [patent_app_number] => 17/844898 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 41 [patent_no_of_words] => 6530 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 570 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844898
Memory device using semiconductor element Jun 20, 2022 Issued
Array ( [id] => 19357002 [patent_doc_number] => 12057459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/830546 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 120 [patent_no_of_words] => 45893 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830546
Semiconductor device Jun 1, 2022 Issued
Array ( [id] => 17855236 [patent_doc_number] => 20220285279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/750423 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750423
Semiconductor structure and manufacturing method thereof May 22, 2022 Issued
Array ( [id] => 18349580 [patent_doc_number] => 20230137691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => HYBRID ORGANIC AND NON-ORGANIC INTERPOSER WITH EMBEDDED COMPONENT IN MOLDING STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/748345 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748345
HYBRID ORGANIC AND NON-ORGANIC INTERPOSER WITH EMBEDDED COMPONENT IN MOLDING STRUCTURE AND METHODS FOR FORMING THE SAME May 18, 2022 Pending
Array ( [id] => 18255373 [patent_doc_number] => 20230082412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/747131 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747131
Semiconductor package May 17, 2022 Issued
Array ( [id] => 20869873 [patent_doc_number] => 12696792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/743451 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 1970 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743451
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME May 12, 2022 Issued
Array ( [id] => 18743427 [patent_doc_number] => 20230352415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MACROCHIP WITH INTERCONNECT STACK FOR POWER DELIVERY AND SIGNAL ROUTING [patent_app_type] => utility [patent_app_number] => 17/730765 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730765
MACROCHIP WITH INTERCONNECT STACK FOR POWER DELIVERY AND SIGNAL ROUTING Apr 26, 2022 Pending
Array ( [id] => 19872466 [patent_doc_number] => 12265326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Method for reducing lithography defects and pattern transfer [patent_app_type] => utility [patent_app_number] => 17/724898 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 1 [patent_no_of_words] => 5294 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724898
Method for reducing lithography defects and pattern transfer Apr 19, 2022 Issued
Array ( [id] => 17780492 [patent_doc_number] => 20220246842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => METHOD FOR MANUFACTURING A MAGNETIC RANDOM-ACCESS MEMORY DEVICE USING POST PILLAR FORMATION ANNEALING [patent_app_type] => utility [patent_app_number] => 17/721369 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721369
Method for manufacturing a magnetic random-access memory device using post pillar formation annealing Apr 14, 2022 Issued
Array ( [id] => 17780204 [patent_doc_number] => 20220246554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => MICROELECTRONIC DEVICES DESIGNED WITH COMPOUND SEMICONDUCTOR DEVICES AND INTEGRATED ON AN INTER DIE FABRIC [patent_app_type] => utility [patent_app_number] => 17/721241 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721241
MICROELECTRONIC DEVICES DESIGNED WITH COMPOUND SEMICONDUCTOR DEVICES AND INTEGRATED ON AN INTER DIE FABRIC Apr 13, 2022 Abandoned
Array ( [id] => 18712770 [patent_doc_number] => 20230335403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/659014 [patent_app_country] => US [patent_app_date] => 2022-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659014
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Apr 12, 2022 Pending
Array ( [id] => 20204101 [patent_doc_number] => 12406884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Self field-suppression CVD tungsten (W) fill on PVD W liner [patent_app_type] => utility [patent_app_number] => 17/718242 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718242
Self field-suppression CVD tungsten (W) fill on PVD W liner Apr 10, 2022 Issued
Array ( [id] => 19567712 [patent_doc_number] => 12142490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Performing annealing process to improve Fin quality of a FinFET semiconductor [patent_app_type] => utility [patent_app_number] => 17/717375 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9671 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/717375
Performing annealing process to improve Fin quality of a FinFET semiconductor Apr 10, 2022 Issued
Array ( [id] => 18379771 [patent_doc_number] => 20230154860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => SEMICONDUCTOR CHIP INCLUDING ALIGN MARK PROTECTION PATTERN AND SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP INCLUDING THE ALIGN MARK PROTECTION PATTERN [patent_app_type] => utility [patent_app_number] => 17/707619 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707619
SEMICONDUCTOR CHIP INCLUDING ALIGN MARK PROTECTION PATTERN AND SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP INCLUDING THE ALIGN MARK PROTECTION PATTERN Mar 28, 2022 Abandoned
Array ( [id] => 18540872 [patent_doc_number] => 20230245983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/701253 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701253
Semiconductor device Mar 21, 2022 Issued
Array ( [id] => 18653131 [patent_doc_number] => 20230298971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MICROELECTRONIC STRUCTURE INCLUDING CONDUCTIVE POLYMER IN TRENCHES OF A CORE SUBSTRATE, AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/699031 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699031
MICROELECTRONIC STRUCTURE INCLUDING CONDUCTIVE POLYMER IN TRENCHES OF A CORE SUBSTRATE, AND METHOD OF MAKING SAME Mar 17, 2022 Pending
Array ( [id] => 19610923 [patent_doc_number] => 12159804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Tungsten molybdenum structures [patent_app_type] => utility [patent_app_number] => 17/654077 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654077
Tungsten molybdenum structures Mar 8, 2022 Issued
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